Axi DMA IP core operation process

• Direct register mode

visit DMACR,SA,DA,length Register initialization DMA transmission , When the transfer is complete , Of related channels DMASR.IOC_Irq It works （ The premise is to enable the interrupt ,DMACR.IOC_IrqEn Can make ）.

MM2S Channel start process ：

1. MM2S_DMACR.RS=1, function DMA
2. Can make MM2S_DMACR.IOC_IrqEn and MM2S_DMACR.Err_IrqEn
3. Configure valid MM2S_SA and MM2S_SA_MSB register
4. Write a non-zero value to MM2S_LENGTH register , Start reading DDR Sent to the AXIS port . This value is the number of bytes read from memory

S2MM Channel start process ：

1. S2MM_DMACR.RS=1, function DMA
2. Can make S2MM_DMACR.IOC_IrqEn and S2MM_DMACR.Err_IrqEn
3. Configure valid S2MM_DA and S2MM_SA_MSB register
4. Write a non-zero value to S2MM_LENGTH register , start-up AXIS Port data write DDR. This value must be greater than or equal to the number of bytes of a packet of data .

In direct register mode , The above startup process needs to be recycled , Every time I read and write , The above registers need to be reconfigured .

The end of each process , An interrupt notification will occur CPU Data operation completed , need CPU eliminate IOC_Irq Register interrupt flag .

• SG Pattern

After configuring control registers and descriptors ,SG mode . Can greatly improve DMA performance .

MM2S Channel start process ：

1. To configure MM2S_CURDESC and MM2S_CURDESC_MSB register , Write the address of the start operator .
2. To configure MM2S_DMACR.RS=1, function DMA
3. register MM2S_DMACR.IOC_IrqEn and MM2S_DMACR.Err_IrqEn Can make
4. To configure MM2S_TAILDESC and MM2S_TAILDESC_MSB, here DMA Start reading descriptors in memory
5. DMA Automatically process operators and read memory data through AXIS Port output

S2MM Channel start process ：

1. To configure S2MM_CURDESC and S2MM_CURDESC_MSB register , Write the address of the start operator .
2. To configure S2MM_DMACR.RS=1, function DMA
3. register S2MM_DMACR.IOC_IrqEn and S2MM_DMACR.Err_IrqEn Can make
4. To configure S2MM_TAILDESC and S2MM_TAILDESC_MSB, here DMA Start reading descriptors in memory
5. DMA Automatically process operators and receive AXIS Port data is written to memory

The end of each process （DMA Received with EOF The operator of ）,DMA Generate interrupt to CPU, need CPU eliminate IOC_Irq Register interrupt flag , Re operate the above process .

• loop DMA Pattern

In this mode ,DMA Can handle the same buffer descriptor , There is no interruption . In this mode DMA Keep working , Unless an abnormal stop or reset occurs .

The key to this model is ,tail Descriptor pointing first The descriptor . Set up Cyclic BD Enable by 1（ Need to be in DMA Configure before running ）.

The rest of the process is the same as SG The pattern is the same .