[FPGA] design and implementation of frequency division and doubling based on FPGA

stay FPGA Used in programming PLL It is the most convenient choice for frequency division and frequency doubling, and can generate the frequency pulse you want , The counter can also be used for frequency division and frequency multiplication

1、 frequency division

1. Frequency division coefficient mode

module pll #(
    parameter SYS_FREQ = 26'd50_000_000,
              OUT_FREQ = 20'd500_000
)
( 
    input				clk		,
    input				rst_n	

);								 
    // Parameters are defined  
                        
    // Intermediate signal definition  
    reg                     clk_500k;	 
    wire [25:0]             coef    ;
    reg  [25:0]             cnt_500k;
    assign coef = (SYS_FREQ/OUT_FREQ) >>1;


always @(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin
        cnt_500k <= 26'b1;
        clk_500k <= 1'b0;
    end 
    else if(cnt_500k < coef)begin 
        cnt_500k <= cnt_500k +26'd1;
    end 
    else if(cnt_500k == coef)begin
        clk_500k <= ~clk_500k;
        cnt_500k <= 26'b1;
    end
    else begin 
        cnt_500k <= cnt_500k;
    end 
end

In this way, the clock frequency of the module and the clock frequency obtained by frequency division shall be given , Calculate the division coefficient and use the counter to get the desired clock frequency , The disadvantage of the clock obtained by frequency division at that time is that the division between the clock frequency of some modules and the clock frequency obtained will be rounded , The error is too obvious , This method can be used to calculate the baud rate of the serial port , After all, the serial port will not transmit one byte of data for long .

2. Even frequency division

2 frequency division

module pll
( 
    input				clk		,
    input				rst_n	

);								 
    // Parameters are defined  
     parameter   num = 8'd2;                   
    // Intermediate signal definition  
    wire [7:0]              num_r       ;
    reg                     clk_out     ;
    reg  [7:0]              cnt         ;
    
assign  num_r = num>>1;

always @(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin
        clk_out <= 1'b0;
        cnt <= 8'd1;
    end 
    else if(cnt == num_r)begin
        clk_out <= ~clk_out;
        cnt <= 8'd1;
    end
    else if(cnt <= num_r)begin
        cnt <= cnt+8'd1;
    end
    else begin 
        clk_out <= clk_out;
        cnt <= cnt;
    end 
end


                        
endmodule

2. Odd frequency division

7 frequency division

module pll
( 
    input				clk		,
    input				rst_n	

);								 
    // Parameters are defined  
     parameter   num = 8'd7;                   
    // Intermediate signal definition  
    wire [7:0]              num_r       ;
    reg                     clk_p       ;
    reg                     clk_n       ;
    wire                    clk_out     ;
    reg  [7:0]              cnt1        ;
    reg  [7:0]              cnt2        ;
    
assign  num_r = num>>1;

always @(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin
        clk_p <= 1'b0;
        cnt1 <= 8'd1;
    end 
    else if(cnt1 <= num)begin
        cnt1 <= cnt1+8'd1;
    if(cnt1 == num_r || cnt1 == num)begin
        clk_p <= ~clk_p;
        if(cnt1 == num)
        cnt1 <= 8'd1;
        else
        ;
    end
    end
    else begin 
        clk_p <= clk_p;
        cnt1 <= cnt1;
    end 
end

always @(negedge clk )begin 
    if(!rst_n)begin
        clk_n <= 1'b0;
        cnt2 <= 8'd1;
    end 

    else if(cnt2 <= num)begin
     cnt2 <= cnt2+8'd1;
    if(cnt2 == num_r || cnt2 == num )begin
        clk_n <= ~clk_n;
        if(cnt2 == num)
        cnt2 <= 8'd1;
        else
        ;
    end
    end
    else begin 
        cnt2 <= cnt2;
        clk_n <= clk_n;
    end 
end

assign clk_out =  clk_p & clk_n;


                        
endmodule

2、 frequency doubling

Recommended or used pll, The signal changes according to the rising or falling edge of the clock , Dividing a cycle clock into two cycles is equivalent to changing four times , But I don't know how to double the frequency when a cycle clock goes up or down , On the Internet, we also use combinatorial logic XOR to multiply frequency , I tried it too. , In this way, it will return to the previous state immediately after the change , Less than a quarter of a clock , I didn't make it , Either it is timescale Set precision units , But this kind of writing is too impractical to suggest , Or use it pll, Otherwise design pll What are you doing here , There is also the recent use of domestic FPGA, With Gaoyun 、 Elins platform , Because we should also contact Fudan micro , I found these frequency stations pll There are errors , Domestic platforms are very troublesome , Maybe you are not familiar with it , The other is that the software of elans runs too slowly , Easily unresponsive , But elynx FAE、 The engineer was OK just at night 11. I also called back my question .

3、tb Program

`timescale 1ns/1ns
                
module pll_tb();
// Excitation signal definition  
reg				tb_clk  	;
reg				tb_rst_n	;

                                      
// Clock cycle parameter definition  
    parameter		CLOCK_CYCLE = 20;    
                                          
pll u_pll(			      
.clk			(tb_clk			),			      
.rst_n		    (tb_rst_n		)		      			      
);
// Make a clock  
initial 		tb_clk = 1'b0;		       		
always #(CLOCK_CYCLE/2) tb_clk = ~tb_clk;  		
                                                
// Generate incentives  
initial  begin						       		
    tb_rst_n = 1'b1;																
    #(CLOCK_CYCLE*2);				            
    tb_rst_n = 1'b0;							
    #(CLOCK_CYCLE*20);				            
    tb_rst_n = 1'b1;							
                                                
                                                
                                                
end 									       	
endmodule