Modelsim and quartus jointly simulate PLL FIFO and other IP cores

Joint simulation steps ：

1、quartus Build a project ****

module pll(
    input   clk,
    input   rst_n,
    output  clk_45p   ,
    output  clk_90p   ,
    output  clk_135p  ,
    output  clk_180p  ,
    output  clk_n45p  ,
    output  clk_n90p  ,
    output  clk_n135p ,
    output  clk_n180p
);

pll_clk u_pll_clk(
	.refclk  (clk      ),// refclk.clk
	.rst     (~rst_n   ),// reset.reset
	.outclk_0(clk_45p  ),// outclk0.clk
	.outclk_1(clk_90p  ),// outclk1.clk
	.outclk_2(clk_135p ),// outclk2.clk
	.outclk_3(clk_180p ),// outclk3.clk
	.outclk_4(clk_n45p ),// outclk4.clk
	.outclk_5(clk_n90p ),// outclk5.clk
	.outclk_6(clk_n135p),// outclk6.clk
	.outclk_7(clk_n180p) // outclk7.clk
	);


endmodule

2、 After setting up the project , Compiler Engineering
3、 Write test files

`timescale 1 ns/1 ns

module tb_pll();

// Clock and reset 
reg clk  ;
reg rst_n;

// Clock cycle , Unit is ns, You can modify the clock cycle here .
parameter CYCLE    = 10;

// Reset time , At this time, it means reset 3 The time of a clock cycle .
parameter RST_TIME = 20 ;


pll u_pll(
   .clk      (clk      ),
   .rst_n    (rst_n    ),
   .clk_45p  (clk_45p  ),
   .clk_90p  (clk_90p  ),
   .clk_135p (clk_135p ),
   .clk_180p (clk_180p ),
   .clk_n45p (clk_n45p ),
   .clk_n90p (clk_n90p ),
   .clk_n135p(clk_n135p),
   .clk_n180p(clk_n180p)
);


// Generate local clock 50M
initial begin
    clk = 0;
    forever
    #(CYCLE/2)
    clk=~clk;
end

// Generate reset signal 
initial begin
    rst_n = 1;
    #2;
    rst_n = 0;
    #(CYCLE*RST_TIME);
    rst_n = 1;
end


endmodule

4、 Select emulator and simulation file

5、 Run the test
6、 Produce results
pll Simulation results

bt1120 Interface FIFO Simulation results