Verilog Instance array
For a well-defined simple module, Such as adder , If we want to instantiate it dozens or hundreds of times , And these instantiations are basically the same form , So we certainly can't instantiate them one by one , At this point, we can use an instantiation array to quickly instantiate .
for instance , If we want to achieve the following functions ：
Now that you know how to build a full adder, make 3 instances of it to create a 3-bit binary ripple-carry adder. The adder adds two 3-bit numbers and a carry-in to produce a 3-bit sum and carry out. To encourage you to actually instantiate full adders, also output the carry-out from each full adder in the ripple-carry adder. cout[2] is the final carry-out from the last full adder, and is the carry-out you usually see.
The port definitions given are as follows
module Adder3(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
Then we can first define a one bit addition module with carry
module Adder1(
input a, b, cin,
output cout, sum );
assign {cout,sum} = a + b + cin;
endmodule
Then use the instantiation array syntax
module Adder3(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
Adder1 Adder1[2:0](// Write our instantiated module as three times the bit width of a one bit adder
.a(a),// The bit width of each port is three times that of the original one bit adder
.b(b),
.cin({cout[1:0],cin}),
.cout(cout),
.sum(sum)
);
The above paragraph instantiates three add modular , The names are add_3[0], add_3[1], add_3[2];
From the schematic diagram, we can see that there are three examples Adder1 modular .
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