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[sequential logic circuit] - register

2022-07-24 07:15:00 【Li Yuchen】

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Welcome to learn digital circuit —— Sequential logic circuit .
Here we will explain the digital register 、 shift register 、 Unidirectional shift register and integrated bidirectional shift register 74LS194, I hope that through our study, you will better understand the mystery of digital circuits .

Catalog

One 、 register

1. Digital register

（1） Circuit composition

（2） working process

（3） Analysis of digital registers

2. shift register

（1） Unidirectional shift register

① Circuit composition

② working process

（2） Integrated bidirectional shift register

①74LS194 The physical object and pin arrangement of the chip

②74LS194 The logic function of the chip

One 、 register

In digital circuits , It is often necessary to store data or calculation results temporarily . A circuit that can temporarily store binary data is called register . It consists of a trigger with memory function and a gate circuit . A trigger has only 0 and 1 Two states , Can only store 1 Bit binary code ,n Triggers can be formed to store n Bit binary register . In the clock pulse CP Under control , The register receives the input binary number and stores it . According to different functions , Registers can be divided into Digital register and shift register .

1. Digital register

The digital register has receive 、 Storage and Clear the original data The function of .

（1） Circuit composition

As shown in the figure is a basic RS Trigger and gate circuit 4 Logic circuit diagram of bit digital register .4 individual RS The reset end of the trigger is connected together , As the zeroing end of the register $\overline{CR}$ , $D_{0}\sim D_{3}$ Is the data input of the register , $Q_{0 }\sim Q_{3}$ Is the output of data .

（2） working process

The work of register is divided into two steps ：

① Clear the register first

Add a negative pulse at the reset end before receiving data （ Reset pulse ）, Set all triggers 0, After the reset pulse returns to the high level , Prepare for receiving data .

② Receive pulse control data storage

Receive pulse CP（ Positive pulse ） arrival , Will NAND gate G0~G3 open , Receive input numbers $D_{3}D_{2}D_{1}D_{0}$ . for example , if $D_{3}D_{2}D_{1}D_{0}$ =1101, be G3、G2、G1、G0 Output is 0010, Each trigger is set to 1101, namely $Q_{3}$ $Q_{2}$ $Q_{1}$ $Q_{0}$ =1101, Complete receiving and deposit .

It can be seen that , The above registers are in operation , Input all numbers at the same time $D_{3}D_{2}D_{1}D_{0}$ , And output all numbers at the same time $Q_{3}$ $Q_{2}$ $Q_{1}$ $Q_{0}$ , This digital input 、 The output mode is Parallel input 、 Parallel output The way .

（3） Analysis of digital registers

advantage ： Short storage time 、 Fast .

shortcoming ： After power failure , All the stored numbers are lost .

2. shift register

Shift registers can not only register numbers , It also has a shift function . Shift means that under the control of shift pulse , Trigger left or right adjacent bits in turn transfer digital processing .

The shift register is divided into Unidirectional shift register and Bidirectional shift register .

（1） Unidirectional shift register

① Circuit composition

As shown in the figure, it is JK The trigger consists of 4 Bit unidirectional right shift register . Of each trigger in the figure J、K Both ends are connected with the adjacent lower trigger 、 $\overline{Q}$ End connection , The lowest one on the left JK trigger FF0 Of K Connect a non gate in series at the end, and then connect with J End to end , As the input of receiving external data , each JK Trigger J And K Always in the opposite state , send JK Trigger only has set 0 Harmony 1 The function of . The shift control signal is added to the... Of each trigger at the same time CP End .

② working process

stay CP Under the action of falling edge , The number to be stored is sent to FF0, The status of other triggers is the same as CP The moment before the action is low 1 The state of the bit trigger is the same , That is, the original number in the register is shifted to the right once 1 position .

Next, save the number 1011 For example , analysis 4 Working process of bit shift right register , To deposit digital $D_{3}D_{2}D_{1}D_{0}$ =1011, Generally, register first clear 0, Then the stored number will be changed from high to low According to the shift pulse beat, it is sent to $D_{0}$ End , When the first One CP When the rising edge comes $D_{0}$ =1, be $Q_{3}$ $Q_{2}$ $Q_{1}$ $Q_{0}$ =0001; When the second CP When the rising edge comes , $D_{0}$ =0, $Q_{3}$ $Q_{2}$ $Q_{1}$ $Q_{0}$ =0010, After four shift pulses, the register status is $Q_{3}$ $Q_{2}$ $Q_{1}$ $Q_{0}$ =1011. As shown in the figure ：

（2） Integrated bidirectional shift register

①74LS194 The physical object and pin arrangement of the chip

As shown in the picture 74LS194 The real chip and its pin arrangement ：

$D_{0}\sim D_{3}$ It is a parallel data input ; $D_{SR}$ Is the right shift serial data input , $D_{SL}$ Is the left shift serial data input .

$Q_{0}\sim Q_{3}$ Is the register parallel data output .

$M_{1}$ and $M_{0}$ It is the control end of bidirectional shift register .

②74LS194 The logic function of the chip

As shown in the figure ：

It can be seen from the table that ,74LS194 The chip has the following logic functions ：

Keep function ： When $M_{1}$ = $M_{0}$ =0 when , With or without CP When it works , The contents of the register remain unchanged .

Parallel number setting function ： When $M_{1}$ = $M_{0}$ =1 when , stay CP When the rising edge acts , Send the numbers at the data input side to the register in parallel , send $Q_{3}$ $Q_{2}$ $Q_{1}$ $Q_{0}$ = $D_{3}D_{2}D_{1}D_{0}$ .

Shift right function ： When $M_{1}$ =0、 $M_{0}$ =1 when , In the shift control signal CP When the rising edge acts , The numbers in the register are shifted one bit to the right , And will $D_{SR}$ Deliver to $Q_{3}$ .

Move left function ： When $M_{1}$ =1、 $M_{0}$ =0 when , stay CP When the rising edge acts , The digits in the register are shifted one bit left in turn , And will $D_{SL}$ Deliver to $Q_{3}$ .

Asynchronous reset function ： When $\overline{CR}$ =0 when , Clear directly , Register bits （ $Q_{0}\sim Q_{3}$ ） Are all 0, You cannot set numbers and shift . Only when $\overline{CR}$ =1 when , Registers allow operation .

The next article continues to explain counters 🥰🥰

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