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Implementation of VGA protocol based on FPGA
2022-06-23 04:19:00 【Passing by_ Listen to the rain】
List of articles
One 、VGA principle
（ One ）VGA agreement
VGA(Video Graphics Array) yes IBM stay 1987 Annual follow PS/2 machine ⼀ From the launch of ⼀ Kinds of video , With resolution ⾼、 display ⽰ Fast speed 、 Yan ⾊ Rich and other advantages , In color ⾊ display ⽰ The device field has been ⼴ Universal response ⽤. No ⽀ Hold hot plug , No ⽀ a ⾳ Frequency transmission . about ⼀ Some inlays ⼊ type VGA display ⽰ System , It can be done without ⽤VGA display ⽰ Cards and computers Under the circumstances , Realization VGA The display of the image ⽰ And control .VGA display ⽰ The utility model has the advantages of low cost 、 Simple structure 、 Should be ⽤ The advantages of flexibility .
（ Two ）VGA Port structure
VGA The port is the video output port , The port contains 15 A pin , Here's the picture 
In the commonly used connection method ,15 Inside a pin 5 One is the most important , They include 3 A basic red , green , Three basic blue color lines and two horizontal and vertical control lines .
（ 3、 ... and ）⾊ Color principle
Sanji ⾊ It means through other means ⾊ Mixing ⽆ I can't get it “ basic ⾊” because ⼈ Of ⾁ The eye has perception red 、 green 、 Blue has three different colors ⾊ Pyramidal cells , therefore ⾊ Color space can usually be divided into three basic types ⾊ To express 
Two 、VGA Show colored stripes
- Top level modules
// Top level documents
module vga_top(
input clk ,// Clock signal
input rst_n ,// Reset signal
output wire hsync ,//
output wire vsync ,//
output wire sync ,
output wire [7:0] vga_r ,// Three channels , Red
output wire [7:0] vga_g ,// Three channels , green
output wire [7:0] vga_b ,// Three channels , Blue
output wire vga_blk ,
output wire vga_clk
);
wire [10:0] h_addr ;// Data valid display area row address
wire [10:0] v_addr ;// Data valid display area field address
wire [23:0] data_dis;
// Exemplification
data_gen u_data_gen(
.clk (clk ) ,// Clock signal
.rst_n (rst_n ) ,// Reset signal
.h_addr (h_addr ) ,// Data valid display area row address
.v_addr (v_addr ) ,// Data valid display area field address
.data_dis (data_dis) // Signals to be displayed
);
// Exemplification
vga_ctrl u_vga_ctrl(
.clk (clk ) ,// Clock signal
.rst_n (rst_n ) ,// Reset signal
.data_dis (data_dis) ,// Signals to be displayed
.h_addr (h_addr ) ,// Data valid display area row address
.v_addr (v_addr ) ,// Data valid display area field address
.hsync (hsync ) ,//
.vsync (vsync ) ,//
.sync (sync ) ,
.vga_r (vga_r ) ,// Three channels , Red
.vga_g (vga_g ) ,// Three channels , green
.vga_b (vga_b ) ,// Three channels , Blue
.vga_blk (vga_blk ) ,
.vga_clk (vga_clk ) // The display shows the clock
);
endmodule
- Color bar module
// The data generated
module data_gen(
input clk ,// Clock signal
input rst_n ,// Reset signal
input [10:0] h_addr ,// Data valid display area row address
input [10:0] v_addr ,// Data valid display area field address
output reg [23:0] data_dis // Signals to be displayed
);
// Parameters are defined
parameter BLACK = 24'h000000,
RED = 24'hFF0000,
GREEN = 24'h00FF00,
BLUE = 24'h0000FF,
YELLOW = 24'hFFFF00,
SKY_BLUE = 24'h00FFFF,
PURPLE = 24'hFF00FF,
GRAY = 24'hC0C0C0,
WHITE = 24'hFFFFFF;
// assignment
[email protected](posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_dis <= BLACK;
end
else begin
case(h_addr)
0 : data_dis <= BLUE ;
80 : data_dis <= RED ;
160 : data_dis <= GREEN ;
240 : data_dis <= BLUE ;
320 : data_dis <= YELLOW ;
400 : data_dis <= SKY_BLUE ;
480 : data_dis <= PURPLE ;
560 : data_dis <= GRAY ;
default: data_dis <= data_dis ;
endcase
end
end
endmodule
- VGA Display module
//VGA Show , Training explanation
`define vga_640_480
`include "vga_para.v"
module vga_ctrl(
input clk ,// Clock signal
input rst_n ,// Reset signal
input [23:0] data_dis,// Signals to be displayed
output reg [10:0] h_addr ,// Data valid display area row address
output reg [10:0] v_addr ,// Data valid display area field address
output reg hsync ,// Line sync
output reg vsync ,// Field synchronization signal
output sync ,
output reg [7:0] vga_r ,// Three channels , Red
output reg [7:0] vga_g ,// Three channels , green
output reg [7:0] vga_b ,// Three channels , Blue
output reg vga_blk ,// Composite blank signal control signal ,VGA When the blanking signal displays data, it is 1 Electricity , Other times it is low level
output vga_clk // The display shows the clock
);
// Parameters are defined
parameter H_SYNC_STA = 1 ;
parameter H_SYNC_STO = `H_Sync_Time ;
parameter H_Data_STA = `H_Sync_Time + `H_Back_Porch + `H_Left_Border;
parameter H_Data_STO = `H_Sync_Time + `H_Back_Porch + `H_Left_Border + `H_Data_Time;
parameter V_SYNC_STA = 1 ;
parameter V_SYNC_STO = `V_Sync_Time ;
parameter V_Data_STA = `V_Sync_Time + `V_Back_Porch + `V_Top_Border;
parameter V_Data_STO = `V_Sync_Time + `V_Back_Porch + `V_Top_Border + `V_Data_Time;
// Signal definition
reg [11:0] cnt_h_addr;// Row address counter
wire add_h_addr;
wire end_h_addr;
reg [11:0] cnt_v_addr;// Field address counter
wire add_v_addr;
wire end_v_addr;
reg clk_25M ;
assign sync = 1'b0;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
clk_25M <= 1'b0;
end
else begin
clk_25M <= ~clk_25M;
end
end
assign vga_clk = clk_25M;
//cnt_h_addr
[email protected](posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
cnt_h_addr <= 12'd0;
end
else if(add_h_addr) begin
if(end_h_addr)begin
cnt_h_addr <= 12'd0;
end
else begin
cnt_h_addr = cnt_h_addr + 12'd1;
end
end
else begin
cnt_h_addr <= 12'd0;
end
end
assign add_h_addr = 1'b1;// Opening conditions
assign end_h_addr = add_h_addr && cnt_h_addr >= `H_Total_Time - 1;
//cnt_v_addr
[email protected](posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
cnt_v_addr <= 12'd0;
end
else if(add_v_addr) begin
if(end_v_addr)begin
cnt_v_addr <= 12'd0;
end
else begin
cnt_v_addr = cnt_v_addr + 12'd1;
end
end
else begin
cnt_v_addr = cnt_v_addr;
end
end
assign add_v_addr = end_h_addr;
assign end_v_addr = add_v_addr && cnt_v_addr >= `V_Total_Time - 1;
// Line sync
[email protected](posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
hsync <= 1'b1;
end
else if(cnt_h_addr == H_SYNC_STA -1)begin
hsync <= 1'b0;
end
else if(cnt_h_addr == H_SYNC_STO - 1) begin
hsync <= 1'b1;
end
else begin
hsync <= hsync ;
end
end
// Field synchronization signal
[email protected](posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
vsync <= 1'b1;
end
else if(cnt_v_addr == V_SYNC_STA -1)begin
vsync <= 1'b0;
end
else if(cnt_v_addr == V_SYNC_STO - 1) begin
vsync <= 1'b1;
end
else begin
vsync <= vsync ;
end
end
// Data valid display area definition
[email protected](posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
h_addr <= 11'd0;
end
else if ((cnt_h_addr >= H_Data_STA - 1 )&&(cnt_h_addr <= H_Data_STO -1)) begin
h_addr <= cnt_h_addr - H_Data_STA -1 ;
end
else begin
h_addr <= 11'd0;
end
end
// Field address valid display area definition
[email protected](posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
v_addr <= 11'd0;
end
else if ((cnt_v_addr >= V_Data_STA - 1 )&& (cnt_v_addr <= V_Data_STO -1)) begin
v_addr <= cnt_v_addr - V_Data_STA -1 ;
end
else begin
v_addr <= 11'd0;
end
end
// Display the data
[email protected](posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
vga_r <= 8'd0;
vga_b <= 8'd0;
vga_g <= 8'd0;
vga_blk <= 1'b0;
end
else if((cnt_h_addr >= H_Data_STA - 1 )&&(cnt_h_addr <= H_Data_STO -1)
&& (cnt_v_addr >= V_Data_STA - 1 )&& (cnt_v_addr <= V_Data_STO -1))begin
vga_r <= data_dis[23:16];//data_dis[23-:8]
vga_g <= data_dis[15:8] ;//data_dis[15-:8]
vga_b <= data_dis[7:0] ;//data_dis[7- :8]
vga_blk <= 1'b1;
end
else begin
vga_r <= 8'd0;
vga_b <= 8'd0;
vga_g <= 8'd0;
vga_blk <= 1'b0;
end
end
endmodule
- Parameter module
`define vga_640_480
`define vga_1920_1080
`define vga_1024_768
`ifdef vga_640_480 // Perform the operation B
`define H_Right_Border 8 // Line synchronization right edge signal
`define H_Front_Porch 8 // The leading edge signal period of line synchronization is long
`define H_Sync_Time 96 // The period of line synchronization signal is long
`define H_Back_Porch 40 // The signal period of the trailing edge of line synchronization is long
`define H_Left_Border 4 // Line sync left edge signal
`define H_Data_Time 640 // The line display cycle is long
`define H_Total_Time 800
`define V_Bottom_Border 8 // Field synchronous bottom edge signal
`define V_Front_Porch 2 // The signal period at the front of field synchronization is long
`define V_Sync_Time 2 // The period of field synchronization signal is long
`define V_Back_Porch 25 // The signal period at the trailing edge of field synchronization is long
`define V_Top_Border 8 // Field synchronous top edge signal
`define V_Data_Time 480 // Long field display period
`define V_Total_Time 525
`elsif vga_1920_1080 // Perform the operation B
`define H_Right_Border 0
`define H_Front_Porch 88
`define H_Sync_Time 44
`define H_Back_Porch 148
`define H_Left_Border 0
`define H_Data_Time 1920
`define H_Total_Time 2200
`define V_Bottom_Border 0
`define V_Front_Porch 4
`define V_Sync_Time 5
`define V_Back_Porch 36
`define V_Top_Border 0
`define V_Data_Time 1080
`define V_Total_Time 1125
`elsif vga_1024_768
`define H_Right_Border 0
`define H_Front_Porch 24
`define H_Sync_Time 136
`define H_Back_Porch 160
`define H_Left_Border 0
`define H_Data_Time 1024
`define H_Total_Time 1344
`define V_Bottom_Borde 0
`define V_Front_Porch 3
`define V_Sync_Time 6
`define V_Back_Porch 29
`define V_Top_Border 0
`define V_Data_Time 768
`define V_Total_Time 806
`else // There can be no
`endif
Results show ：
3、 ... and 、VGA Show characters
The code is as follows ：
module VGA_test(
OSC_50, // primary CLK2_50 Clock signal
VGA_CLK, //VGA Self clock
VGA_HS, // Line sync
VGA_VS, // Field synchronization signal
VGA_BLANK, // Composite blank signal control signal When BLANK It is the blanking level of analog video output at low level , At that moment, from R9~R0,G9~G0,B9~B0 All data entered is ignored
VGA_SYNC, // In accordance with the synchronization control signal Both line timing and field timing should generate synchronization pulses
VGA_R, //VGA green
VGA_B, //VGA Blue
VGA_G); //VGA green
input OSC_50; // External clock signal CLK2_50
output VGA_CLK,VGA_HS,VGA_VS,VGA_BLANK,VGA_SYNC;
output [7:0] VGA_R,VGA_B,VGA_G;
parameter H_FRONT = 16; // The leading edge signal period of line synchronization is long
parameter H_SYNC = 96; // The period of line synchronization signal is long
parameter H_BACK = 48; // The signal period of the trailing edge of line synchronization is long
parameter H_ACT = 640; // The line display cycle is long
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK; // The total period of line blank signal is long
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT; // The total line cycle is long and time-consuming
parameter V_FRONT = 11; // The signal period at the front of field synchronization is long
parameter V_SYNC = 2; // The period of field synchronization signal is long
parameter V_BACK = 31; // The signal period at the trailing edge of field synchronization is long
parameter V_ACT = 480; // Long field display period
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK; // The total period of field blank signal is long
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT; // The total period of the field is long and time-consuming
reg [10:0] H_Cont; // Line cycle counter
reg [10:0] V_Cont; // Field period counter
wire [7:0] VGA_R; //VGA Red control line
wire [7:0] VGA_G; //VGA Green control line
wire [7:0] VGA_B; //VGA Blue control line
reg VGA_HS;
reg VGA_VS;
reg [10:0] X; // The number of pixels in the current line
reg [10:0] Y; // Which line of the current field
reg CLK_25;
[email protected](posedge OSC_50)
begin
CLK_25=~CLK_25; // The clock
end
assign VGA_SYNC = 1'b0; // Synchronization signal low level
assign VGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK)); // When the row counter is less than the total length of the row blank or the field counter is less than the total length of the field blank , Blank signal low level
assign VGA_CLK = ~CLK_to_DAC; //VGA The clock is equal to CLK_25 Take the opposite
assign CLK_to_DAC = CLK_25;
[email protected](posedge CLK_to_DAC)
begin
if(H_Cont<H_TOTAL) // If the row counter is less than the total row time
H_Cont<=H_Cont+1'b1; // Row counter +1
else H_Cont<=0; // Otherwise, the line counter is cleared
if(H_Cont==H_FRONT-1) // If the row counter is equal to the blank time at the leading edge of the row -1
VGA_HS<=1'b0; // The line synchronization signal is set to 0
if(H_Cont==H_FRONT+H_SYNC-1) // If the row counter is equal to the row leading edge + Line synchronization -1
VGA_HS<=1'b1; // The line synchronization signal is set to 1
if(H_Cont>=H_BLANK) // If the row counter is greater than or equal to the total length of row blank
X<=H_Cont-H_BLANK; //X Equal to the row counter - Total length of blank lines （X Is the number of pixels in the current line ）
else X<=0; // otherwise X by 0
end
[email protected](posedge VGA_HS)
begin
if(V_Cont<V_TOTAL) // If the field counter is less than the total row time
V_Cont<=V_Cont+1'b1; // Field counter +1
else V_Cont<=0; // Otherwise, the field counter is cleared
if(V_Cont==V_FRONT-1) // If the field counter is equal to the field leading edge blank time -1
VGA_VS<=1'b0; // The field synchronization signal is set to 0
if(V_Cont==V_FRONT+V_SYNC-1) // If the field counter is equal to the leading edge of the row + Field synchronization -1
VGA_VS<=1'b1; // The field synchronization signal is set to 1
if(V_Cont>=V_BLANK) // If the field counter is greater than or equal to the total time of field blank
Y<=V_Cont-V_BLANK; //Y Equal to the field counter - Total duration of field blank （Y For the line number of the current field ）
else Y<=0; // otherwise Y by 0
end
reg valid_yr;
[email protected](posedge CLK_to_DAC)
if(V_Cont == 10'd32) // Field counter =32 when
valid_yr<=1'b1; // Line input activates
else if(V_Cont==10'd512) // Field counter =512 when
valid_yr<=1'b0; // Line input freeze
wire valid_y=valid_yr; // attachment
reg valid_r;
[email protected](posedge CLK_to_DAC)
if((H_Cont == 10'd32)&&valid_y) // Row counter =32 when
valid_r<=1'b1; // Pixel input active
else if((H_Cont==10'd512)&&valid_y) // Row counter =512 when
valid_r<=1'b0; // Pixel input is frozen
wire valid = valid_r; // attachment
wire[10:0] x_dis; // Pixel display control signal
wire[10:0] y_dis; // The line shows the control signal
assign x_dis=X; // attachment X
assign y_dis=Y; // attachment Y
parameter // Dot matrix font ： Every line char_lineXX Is a line displayed , common 272 Column
char_line00=272'h00000000000000000000000000000000000000000000000000000000000000000000, // The first 1 That's ok
char_line01=272'h00000000000000000000000000000000000000000000000000000000000000000000, // The first 2 That's ok
char_line02=272'h00000000000000000000000000000000, // The first 3 That's ok
char_line03=272'h00000000000000000000000000000000, // The first 4 That's ok
char_line04=272'h00000000000000000000000000000000, // The first 5 That's ok
char_line05=272'h7E7EFE00183C0838187E183818083C3C, // The first 6 That's ok
char_line06=272'h84849200244238442442244424384242, // The first 7 That's ok
char_line08=272'h04041000400208424204424242080202, // The first 9 That's ok
char_line07=272'h08081000404208424204424242084242, // The first 8 That's ok
char_line09=272'h080810005C0408424208424242080404, // The first 10 That's ok
char_line0a=272'h1010107E621808464208424642081818, // The first 11 That's ok
char_line0b=272'h202010004204083A4210423A42080404, // The first 12 That's ok
char_line0c=272'h20201000420208024210420242080202, // The first 13 That's ok
char_line0d=272'h42421000424208024210420242084242, // The first 14 That's ok
char_line0e=272'h42421000224208242410242424084242, // The first 15 That's ok
char_line0f=272'hFCFC38001C3C3E1818101818183E3C3C, // The first 16 That's ok
char_line10=272'h00000000000000000000000000000000, // The first 17 That's ok
char_line11=272'h00000000000000000000000000000000, // The first 18 That's ok
reg[8:0] char_bit;
[email protected](posedge CLK_to_DAC)
if(X==10'd144)char_bit<=9'd272; // When displayed to 144 Pixel ready to start outputting image data
else if(X>10'd144&&X<10'd416) // Left margin screen 144 Pixels to 416 When the pixel 416=144+272（ The width of the image ）
char_bit<=char_bit-1'b1; // Output image information upside down
reg[29:0] vga_rgb; // Define color cache
[email protected](posedge CLK_to_DAC)
if(X>10'd144&&X<10'd416) //X Controls the horizontal display boundary of the image ： Left margin to the left of the screen 144 Pixels The right boundary is away from the left boundary of the screen 416 Pixels
begin case(Y) //Y Controls the vertical display boundary of the image ： From the top of the screen 160 Pixels begin to display the first row of data
10'd160:
if(char_line00[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000; // If the row has data The color is red
else vga_rgb<=30'b0000000000_0000000000_0000000000; // Otherwise black
10'd162:
if(char_line01[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd163:
if(char_line02[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd164:
if(char_line03[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd165:
if(char_line04[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd166:
if(char_line05[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd167:
if(char_line06[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd168:
if(char_line07[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd169:
if(char_line08[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd170:
if(char_line09[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd171:
if(char_line0a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd172:
if(char_line0b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd173:
if(char_line0c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd174:
if(char_line0d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd175:
if(char_line0e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd176:
if(char_line0f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd177:
if(char_line10[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd178:
if(char_line11[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd179:
if(char_line12[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd180:
if(char_line13[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd181:
if(char_line14[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd182:
if(char_line15[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd183:
if(char_line16[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd184:
if(char_line17[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd185:
if(char_line18[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd186:
if(char_line19[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd187:
if(char_line1a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd188:
if(char_line1b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd189:
if(char_line1c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd190:
if(char_line1d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd191:
if(char_line1e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd192:
if(char_line1f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
default:vga_rgb<=30'h0000000000; // Default color black
endcase
end
else vga_rgb<=30'h000000000; // Otherwise black
assign VGA_R=vga_rgb[23:16];
assign VGA_G=vga_rgb[15:8];
assign VGA_B=vga_rgb[7:0];
endmodule
Results show ：
Reference resources
https://blog.csdn.net/cchulu/article/details/73876978
https://blog.csdn.net/weixin_56102526/article/details/124964347
https://blog.csdn.net/cchulu/article/details/73876978
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