[datasheet phy] interpretation of ksz8081 data manual

Ksz8081 At present for MICROCHIP The strength of PHY One chip , originally MICREL Company design ;

The chip is divided into MII Interface model ,RMII Interface model , There are two different product models , Pay attention to the chip suffix when designing and selecting , The price is also different .

10/100M The adaptive ;

MDC/MDIO Management Interface;

Power supply ：3.3V

encapsulation ：24-pin 4 mm x 4 mm QFN Package

MII Interface ：

RMII Interface ：

Model selection parameters

Mainly external crystal oscillator A： can 25M Access , Internal frequency doubling 50M Output ;D： It must be externally connected 50M Active crystal oscillator ; Temperature range ： Commercial grade , Industrial grade ; On the right is the specific model ;

MII and RMII For an introduction, see ：

[Datasheet] PHY LAN8720 Network chip interpretation

MII need CRS and COL Monitor the carrier signal to determine whether there is data coming from the network port ;

RMII send PHY And MAC Synchronized the clock , Data can be read directly ;

1、 Introduction to block diagram , Conventional connection ,RMII Interface ,50M The clock is synchronized to MCU Of MAC controller ;

【 Tips 】： Here in the debugging driver , Special attention should be paid to the external crystal oscillator 25MHZ, still 50MHZ Active crystal oscillator , Although you can output 50MHZ Clock source to MCU; But yes. PHY Of 1Fh – PHY Control 2 The storage clock should be configured correctly ;

According to the selected chip model , External grounding 25M perhaps 50M, The configuration needs to be correct ,PHY To work properly , I didn't care about this when debugging this chip , Think and ordinary PHY equally ;

2、PHY Address , It can be set by hardware , There are two address bits , Range 0~3;

3、 Key pin description , These lines are mainly used for sending and receiving data ;

4、 Hardware design block diagram

25M Crystal oscillator design

50M Crystal oscillator design

Multiple PHY The chip shares a clock source

4、MDC sequential ,32 Bit data parsing

5、 Power and ground parameter diagram

6、PHY register , among 0x1E and 0x1F This chip expands , Other and ordinary PHY Agreement ;

6.1 Basic Control For settings PHY Work 10/100M, Self testing / Normal mode, etc ;

6.2 Basic Status For reading PHY state , Identify the network cable bandwidth ,Link State, etc ;

6.3 PHY Identifier To read the manufacturer OUI, Verifiable MAC And PHY Whether the interaction is normal , The manufacturer information is consistent with the chip manual .

6.4 PHY Control 1 For reading PHY Link state , Operation status and other information ;

6.5 PHY Control 2 The external crystal oscillator type can be set ,LED Information such as light mode ;

Pay attention to WeChat public number , reply “ksz8081”, The chip manual is free to download ;