Detailed explanation of srl16e in xilinxffpga

FPGA The shift register is often used in the development process , The shift register is usually used to beat a signal , Make the timing meet our needs . One of the most common ways to shoot is in process Shift a signal in a procedure statement （ stay verilog It's in always Shift in the process ）.XilinxFPGA A primitive provided in SRL6E, Can be maximized 16 Shift register of shift bit register .  It should be noted that ,SRL16E Primitives may have slightly different forms in different devices , The following is the Artix-7 In a series of devices SRL16E The original language ：

  // SRL16E: 16-bit shift register LUT with clock enable operating
   //         on posedge of clock (Mapped to a SliceM LUT6)
   //         Artix-7
   // Xilinx HDL Language Template, version 2020.1

   SRL16E #(
      .INIT(16'h0000) // Initial Value of Shift Register     Initialize the register 
   ) SRL16E_inst (
      .Q(Q),       // SRL data output   Register output port 
      .A0(A0),     // Select[0] input Four output bits select the control address 
      .A1(A1),     // Select[1] input
      .A2(A2),     // Select[2] input
      .A3(A3),     // Select[3] input
      .CE(CE),     // Clock enable input Register enable port 
      .CLK(CLK),   // Clock input           Clock port 
      .D(D)        // SRL data input     Register input port 
   );

example：

`timescale 1ns / 1ps
module SRL16E_Test(

    input clk_in,
    output 	wResetQ,
    output 	wEnableN
    );

wire wResetQ;
wire wEnableN;


SRL16E #( .INIT( 16'hFF00 ) ) mReset
( .CLK ( clk_in ),
  .CE  ( 1'b1 ),
  .A0  ( 1'b1 ), .A1( 1'b1 ), .A2( 1'b1 ), .A3( 1'b1 ),   // Select the first 16 An output 
  .D   ( 1'b0 ),
  .Q   ( wResetQ ) );


SRL16E #( .INIT( 16'h000F ) ) mEnable
( .CLK ( clk_in ),
  .CE  ( 1'b1 ),
  .A0  ( 1'b1 ), .A1( 1'b1 ), .A2( 1'b1 ), .A3( 1'b1 ),  // Select the first 16 An output 
  .D   ( 1'b1 ),
  .Q   ( wEnableN ) );

endmodule

Testbench:

`timescale 1ns / 1ps
module tb_SRL16E;

    reg		 clk_in;
    wire	wResetQ;
    wire	wEnableN;

    always #10 clk_in <= ~clk_in; 				// Clock signal 50M
    
    initial begin
        clk_in = 1'b1;
    end

    SRL16E_Test u_SRL16E(
        .clk_in   (clk_in   ),
        .wResetQ  (wResetQ  ),
        .wEnableN (wEnableN )
    );

endmodule

Waveform