Digital stopwatch based on Verilog HDL

Tools ：quartus18.1 lite

Code

	module biao_v(clk,reset,pause,msh,msl,sh,sl,minh,minl);
	// among msh It is the ten digits of the hundredth of a second ,msl Is a bit of a hundredth of a second ,sh Is the ten digits of the second ,sl Is a bit of second ,minh Ten points ,minl Is divided into two digits 
	input clk,reset,pause;// The clock , Reset , Pause 
	output [3:0] msh,msl,sh,sl,minh,minl;// Output 
	reg [3:0] msh,msl,sh,sl,minh,minl;// register 
	reg count1,count2;// register 
	
	// Set hundredths of a second 
	always @(posedge clk or posedge reset)// Clock rising edge or reset rising edge 
	 begin
		if(reset)// When the signal is reset 
		 begin
		{msh,msl}<=0;// Ten bits per hundredth of a second and one bit per hundredth of a second 0
		count1<=0;// register count1 Fu 0
		 end
		 else if(!pause)// When the signal is not reset, not pause 
		 begin
			if(msl==9)// If the hundredth of a second is 9
		   begin
				msl<=0;// Hundredths of a second 0
				if(msh==9)// If the tenth digit of a hundredth of a second is 9
				begin
					msh<=0;// Ten bits per hundredth of a second 0
					count1<=1;// register count1 Fu 1
				end
				else// If the tenth digit of a hundredth of a second is not 9
				msh<=msh+1;// Ten digits of a hundredth of a second plus 1
		   end
			else// If the hundredth of a second is not 9
			begin 
				msl<=msl+1;// One hundredth of a second plus 1
				count1<=0;// register coount1 Fu 0
			end
			end
	 end
	 
	 // Set seconds 
	 always @(posedge count1 or posedge reset)// The signal is a register count1 Rising edge or reset rising edge 
	 begin
		if(reset)// The signal is reset 
		begin
			{sh,sl}<=0;// Ten bits and one bit of the second 0
			count2<=0;// register count2 Fu 0
		end
		else if(sl==9)// The bits of seconds are 9
		begin
			sl<=0;// Second bit assignment 0
			if(sh==5)// The tenth digit of a second is 5
			begin
				sh<=0;// Ten bits per second 0
				count2<=1;// register count2 Fu 1
			end
			else // Ten seconds is not 5
				sh<=sh+1;// Ten seconds plus 1
		end
		else// The second bit is not 9
		begin
			sl<=sl+1;// Seconds plus 1
			count2<=0;// register count2 Fu 0
		end
	 end
	 
	 // Set points 
	 [email protected](posedge count2 or posedge reset)// register count2 Rising edge or reset rising edge 
		begin
		if(reset)// The signal is reset 
		begin
			minh<=0;// Ten Fu 0
			minl<=0;// Sub position Fu 0
		end
		else if(minl==9)// The signal is divided into bits 9
		begin
			minl<=0;// Sub position Fu 0
		   if(minh==5)// Ten points are 5
				minh<=0;// Ten Fu 0
				else// Ten is not 5
				minh<=minh+1;// Ten points plus 1
		end
		else// It's not 9 Nor is it reset 
			minl<=minl+1;// Divide by one and add 1
		end
	endmodule

result

From the functional simulation results, we can see , Only ten bits per hundredth of a second have changed
In fact, I know a little about this program myself , I don't know much about the specific principle

Reference resources ：https://blog.csdn.net/qq_43643118/article/details/117031719