(to be optimized and modified) vivado DDR4 SDRAM (MIG) (2.2) IP core learning record

The user interface PAGE 1

  Record according to the serial number in the figure :

1.memory device interface speed

        confirm DDR4 Operating clock of , The box is filled with DDR4 Single clock cycle . for example ,2400P DDR4 The clock rate of is 1200M, The clock period is 833ps.

2.DCI CASCADE（ Digital control impedance ,digitally controlled impendence）

        DCI CASCADE Used to constrain one or more BANK Output impedance , When using this function ,DDR4 The clock cycle of is not less than 938ps, namely DDR The clock is no higher than 1066,DDR4 The throughput rate is not higher than 2133.

3.PHY to controller clock frequency ratio 

        DDR4 Ratio to user interface clock , This value defaults to 4:1. because DDR4 The rising and falling edges of the middle clock are read and written respectively 1 Time （ A single clock totals 2 Time ）, stay 4：1 Under the clock , The user interface needs to be read and written every time 8 Times the data width .

4.reference input clock speed

        Definition DDR4 IP The input reference clock cycle of the core .

5.enable custom parts data file

        When memory part There is no required... In the drop-down options DDR Model time , You can write what you need DDR4 The memory of CSV Parameter file , Import IP Postnuclear , Can from memory part Select the corresponding model .

6.CAS latency and CAS write latency（CL And CWL）

        CL and CWL selective DDR4 Model selection , among CWL It can be downloaded from MR2 Select... Is defined in the register .

7.clamshell topology

        When there are both front and back sides of the circuit board DDR4 When particles （ Image docking ）, Check this option . This mode was chosen for convenience PCB wiring , adopt CS0 and CS1 Control the positive and negative... Respectively DDR4.

 8.slot

         Used for the component Memory module of , Include signal And dual Two kinds of , Not used yet .

9.Data Width

        Selected by DDR The width and quantity of particle data determine , if DDR The particle bit width is 16bit, Co selection 4 slice DDR4, Then the data bit width here is 64.

10.Data Mask and DBI（Data Bus Inversion, basis DDR characteristic ,DBI The significance of existence is to reduce power consumption ）

        basis PG105 Manual selection drop-down box , Current default selection DM NO DBI

11.memory address map

        Select the user input address signal here （app_addr） And DDR controller IP The address signal mapping relation of the core , The default is ROW COLUMN BANK The order of , Here's the picture

      

12.ordering

        Order of command execution , There are two cases ：a.normal, allow DDR IP The core reads the external input commands according to the priority according to the internal controller algorithm 、 Write commands, etc. to reorder ;b.strict, requirement DDR IP The kernel executes the input commands in sequence , It may reduce DDR IP Bandwidth utilization of the core .

13.Force Read and Write commands to use AutoPrecharge,enable autoprecharge input,enable user refresh and ZQCS input

        These three options need to be correct DDR、 Check if you have a deep understanding of your own application , The purpose is to improve the efficiency of reading and writing , Pre charging is controlled by the user 、 Self refresh 、ZQCS Keep the order . When unchecked ,IP Nuclear automatic control precharge 、 Refresh 、ZQCS command , Not checked by default .