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VGA display of de2-115 FPGA development board
2022-06-25 13:44:00 【dedsec0x】
Catalog
One 、VGA brief introduction
VGA(Video Graphics Array) Video graphics array yes IBM On 1987 A use proposed in analog signal Computer display standard .VGA The interface means that the computer adopts VGA Special interface for standard output data .VGA The interface has 15 The needle , Divide into 3 row , Each row 5 Holes , The most widely used interface type on graphics card , Most graphics cards have this interface . It transmits red 、 green 、 blue analog signal as well as Synchronous signal ( Horizontal and vertical signals ).
Color difference of common interfaces VGA Interface (D-Sub Interface )
Speaking of VGA Interface , I believe many friends will not be strange , Because this interface is the most important interface on the computer monitor , From the big CRT The era of display has begun ,VGA Interfaces are used , And it has been used up to now , in addition VGA Interfaces are also known as D-Sub Interface . [2]
Many people think that only HDMI Interface To transmit high-definition signals , But this is a misunderstanding that is easy for everyone to enter , Because by VGA The connection of can also display 1080P Image , Even higher resolution can be achieved , So there's no problem using it to connect display devices to watch HD video , And although it is an analog interface , But because of VGA Decompose the video signal into R、G、B Tricolor sum HV Line field signal transmission , Therefore, the loss in transmission is quite small .
VGA Causes of interface generation : The information processed by the graphics card will eventually be output to the display , The output interface of the graphics card is the bridge between the computer and the display , It is responsible for outputting the corresponding image signal to the display .CRT Monitor For design and manufacturing reasons , Can only accept analog signal Input , This requires the graphics card to output analog signals .VGA The interface is the interface that outputs analog signals on the graphics card ,VGA(Video Graphics Array) Interface , Also called D-Sub Interface . Although the LCD can receive digital signals directly , But many low-end products are designed to match VGA Interface with the graphics card , So we use VGA Interface .
Two 、VGA Implementation code
The code is as follows :
module VGA_test(
OSC_50, // primary CLK2_50 Clock signal
VGA_CLK, //VGA Self clock
VGA_HS, // Line sync
VGA_VS, // Field synchronization signal
VGA_BLANK, // Composite blank signal control signal When BLANK It is the blanking level of analog video output at low level , At that moment, from R9~R0,G9~G0,B9~B0 All data entered is ignored
VGA_SYNC, // In accordance with the synchronization control signal Both line timing and field timing should generate synchronization pulses
VGA_R, //VGA green
VGA_B, //VGA Blue
VGA_G); //VGA green
input OSC_50; // External clock signal CLK2_50
output VGA_CLK,VGA_HS,VGA_VS,VGA_BLANK,VGA_SYNC;
output [7:0] VGA_R,VGA_B,VGA_G;
parameter H_FRONT = 16; // The leading edge signal period of line synchronization is long
parameter H_SYNC = 96; // The period of line synchronization signal is long
parameter H_BACK = 48; // The signal period of the trailing edge of line synchronization is long
parameter H_ACT = 640; // The line display cycle is long
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK; // The total period of line blank signal is long
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT; // The total line cycle is long and time-consuming
parameter V_FRONT = 11; // The signal period at the front of field synchronization is long
parameter V_SYNC = 2; // The period of field synchronization signal is long
parameter V_BACK = 31; // The signal period at the trailing edge of field synchronization is long
parameter V_ACT = 480; // Long field display period
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK; // The total period of field blank signal is long
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT; // The total period of the field is long and time-consuming
reg [10:0] H_Cont; // Line cycle counter
reg [10:0] V_Cont; // Field period counter
wire [7:0] VGA_R; //VGA Red control line
wire [7:0] VGA_G; //VGA Green control line
wire [7:0] VGA_B; //VGA Blue control line
reg VGA_HS;
reg VGA_VS;
reg [10:0] X; // The number of pixels in the current line
reg [10:0] Y; // Which line of the current field
reg CLK_25;
[email protected](posedge OSC_50)
begin
CLK_25=~CLK_25; // The clock
end
assign VGA_SYNC = 1'b0; // Synchronization signal low level
assign VGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK)); // When the row counter is less than the total length of the row blank or the field counter is less than the total length of the field blank , Blank signal low level
assign VGA_CLK = ~CLK_to_DAC; //VGA The clock is equal to CLK_25 Take the opposite
assign CLK_to_DAC = CLK_25;
[email protected](posedge CLK_to_DAC)
begin
if(H_Cont<H_TOTAL) // If the row counter is less than the total row time
H_Cont<=H_Cont+1'b1; // Row counter +1
else H_Cont<=0; // Otherwise, the line counter is cleared
if(H_Cont==H_FRONT-1) // If the row counter is equal to the blank time at the leading edge of the row -1
VGA_HS<=1'b0; // The line synchronization signal is set to 0
if(H_Cont==H_FRONT+H_SYNC-1) // If the row counter is equal to the row leading edge + Line synchronization -1
VGA_HS<=1'b1; // The line synchronization signal is set to 1
if(H_Cont>=H_BLANK) // If the row counter is greater than or equal to the total length of row blank
X<=H_Cont-H_BLANK; //X Equal to the row counter - Total length of blank lines (X Is the number of pixels in the current line )
else X<=0; // otherwise X by 0
end
[email protected](posedge VGA_HS)
begin
if(V_Cont<V_TOTAL) // If the field counter is less than the total row time
V_Cont<=V_Cont+1'b1; // Field counter +1
else V_Cont<=0; // Otherwise, the field counter is cleared
if(V_Cont==V_FRONT-1) // If the field counter is equal to the field leading edge blank time -1
VGA_VS<=1'b0; // The field synchronization signal is set to 0
if(V_Cont==V_FRONT+V_SYNC-1) // If the field counter is equal to the leading edge of the row + Field synchronization -1
VGA_VS<=1'b1; // The field synchronization signal is set to 1
if(V_Cont>=V_BLANK) // If the field counter is greater than or equal to the total time of field blank
Y<=V_Cont-V_BLANK; //Y Equal to the field counter - Total duration of field blank (Y For the line number of the current field )
else Y<=0; // otherwise Y by 0
end
reg valid_yr;
[email protected](posedge CLK_to_DAC)
if(V_Cont == 10'd32) // Field counter =32 when
valid_yr<=1'b1; // Line input activates
else if(V_Cont==10'd512) // Field counter =512 when
valid_yr<=1'b0; // Line input freeze
wire valid_y=valid_yr; // attachment
reg valid_r;
[email protected](posedge CLK_to_DAC)
if((H_Cont == 10'd32)&&valid_y) // Row counter =32 when
valid_r<=1'b1; // Pixel input active
else if((H_Cont==10'd512)&&valid_y) // Row counter =512 when
valid_r<=1'b0; // Pixel input is frozen
wire valid = valid_r; // attachment
wire[10:0] x_dis; // Pixel display control signal
wire[10:0] y_dis; // The line shows the control signal
assign x_dis=X; // attachment X
assign y_dis=Y; // attachment Y
parameter // Dot matrix font : Every line char_lineXX Is a line displayed , common 272 Column
char_line00=272'h0000000000000000000000000000000000000000000000000000000000000000000,
char_line01=272'h0000000000000000000000000000000000000000000000000000000000000000000,
char_line02=272'h0100001000020000020000000000000000000000000000000000000000000000000,
char_line03=272'h00C0001C00030000030000F00000000000000000000000000000000000000000000,
char_line04=272'h006000180001800002001FC00000000000000000000000000000000000000000000,
char_line05=272'h00700018000180000203E0000000000000000000000000000000000000000000000,
char_line06=272'h0030001800008010021000180000000003C00060008000600000000000000000000,
char_line07=272'h00200618000080387FF818180000000006200060018000600000000000000000000,
char_line08=272'h002186183FFFFFFC02020C30000000000C3000E01F8000E00000000000000000000,
char_line09=272'h3FFFC61800200C0002010C3000000000181800E0018000E00000000000000000000,
char_line0a=272'h0006061800200C00020184200000000018180160018001600000000000000000000,
char_line0b=272'h0007061800200C00022184400000000018080160018001600000000000000000000,
char_line0c=272'h0006061800100C003FF0808000000000300C0260018002600000000000000000000,
char_line0d=272'h080C0618001018000200000000000000300C0460018004600000000000000000000,
char_line0e=272'h040C0618001018000200180000000000300C0460018004600000000000000000000,
char_line0f=272'h020C06180018180002027FFC00000000300C0860018008600000000000000000000,
char_line10=272'h01980618000830000209801800000000300C0860018008600000000000000000000,
char_line11=272'h00D80618000C30007FFD001800000000300C1060018010600000000000000000000,
char_line12=272'h00700618000460000219001800000000300C3060018030600000000000000000000,
char_line13=272'h00380618000660000219001800000000300C2060018020600000000000000000000,
char_line14=272'h007C06180002C0000219101800000000300C4060018040600000000000000000000,
char_line15=272'h00CE06180003C0000211F9F800000000300C7FFC01807FFC0000000000000000000,
char_line16=272'h00C7061800018000021100180000000018080060018000600000000000000000000,
char_line17=272'h018386180003C00002B100180000000018180060018000600000000000000000000,
char_line18=272'h030380180006E000027100180000000018180060018000600000000000000000000,
char_line19=272'h06018018000C780002210018000000000C300060018000600000000000000000000,
char_line1a=272'h0C00001800381E0002010018000000000620006003C000600000000000000000000,
char_line1b=272'h1000001800600FC00201FFF80000000003C003FC1FF803FC0000000000000000000,
char_line1c=272'h200001F8018003FC020100180000000000000000000000000000000000000000000,
char_line1d=272'h400000700E0000F0020100180000000000000000000000000000000000000000000,
char_line1e=272'h0000002030000000020200000000000000000000000000000000000000000000000,
char_line1f=272'h0000000000000000000000000000000000000000000000000000000000000000000;
reg[8:0] char_bit;
[email protected](posedge CLK_to_DAC)
if(X==10'd144)char_bit<=9'd272; // When displayed to 144 Pixel ready to start outputting image data
else if(X>10'd144&&X<10'd416) // Left margin screen 144 Pixels to 416 When the pixel 416=144+272( The width of the image )
char_bit<=char_bit-1'b1; // Output image information upside down
reg[29:0] vga_rgb; // Define color cache
[email protected](posedge CLK_to_DAC)
if(X>10'd144&&X<10'd416) //X Controls the horizontal display boundary of the image : Left margin to the left of the screen 144 Pixels The right boundary is away from the left boundary of the screen 416 Pixels
begin
//case(Y)
vga_rgb<=30'b1111111111_1111111111_0000000000; //Y Controls the vertical display boundary of the image : From the top of the screen 160 Pixels begin to display the first row of data
/*
10'd160:
if(char_line00[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000; // If the row has data The color is red
else vga_rgb<=30'b0000000000_0000000000_0000000000; // Otherwise black
10'd162:
if(char_line01[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd163:
if(char_line02[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd164:
if(char_line03[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd165:
if(char_line04[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd166:
if(char_line05[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_z0000000000_0000000000;
10'd167:
if(char_line06[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd168:
if(char_line07[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd169:
if(char_line08[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd170:
if(char_line09[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd171:
if(char_line0a[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd172:
if(char_line0b[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd173:
if(char_line0c[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd174:
if(char_line0d[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd175:
if(char_line0e[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd176:
if(char_line0f[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd177:
if(char_line10[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd178:
if(char_line11[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd179:
if(char_line12[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd180:
if(char_line13[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd181:
if(char_line14[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd182:
if(char_line15[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd183:
if(char_line16[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd184:
if(char_line17[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd185:
if(char_line18[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd186:
if(char_line19[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd187:
if(char_line1a[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd188:
if(char_line1b[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd189:
if(char_line1c[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd190:
if(char_line1d[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd191:
if(char_line1e[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd192:
if(char_line1f[char_bit])vga_rgb<=30'b1111111111_1111111111_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
default:vga_rgb<=30'h0000000000; // Default color black
endcase
*/
end
else vga_rgb<=30'b1111111111_0000000000_1111111111; // Otherwise black
assign VGA_R=vga_rgb[23:16];
assign VGA_G=vga_rgb[15:8];
assign VGA_B=vga_rgb[7:0];
endmodule
Use Chinese character dot matrix to replace Chinese characters in Chinese character code , Then implement VGA Show
3、 ... and 、 Reference blog
Try to use Verilog drive VGA_Joyce_Ng The blog of -CSDN Blog _verilog vga
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