Arm V7 coprocessor

/*
 * 2012/3/29 10:47    qing
 */

Coprocessor

    1.CP14 Debug the communication channel coprocessor

    2.CP15 System control coprocessor

         He uses coprocessor instructions MCR and MRC Provide specific registers to configure and control caches、MMU、 Protection system 、 Configure clock mode （ stay
        bootloader Clock initialization uses ）

        
        |31     28|27  24| 23    21| 20 |19    16|15    12|11      8|7        5|4  | 3    0 |
        ---------------------------------------------------------------------------
        | cond | 1110 | 0 0 0 | 0  | CRn  | Rd    | cp_num | opcode_2| 1 |  CRm      |
        ---------------------------------------------------------------------------
        mcr {<cond>} p15, 0, <Rd>, <CRn>, <CRm>{, <opcode_2>}
        <opcode_1> For ever 0b000, Not for 0 when , The result of the operation is unpredictable .
        <Rd> As a source register ARM register , Its value will be transferred to the coprocessor register of . Not for PC.
        <CRn> The coprocessor registers as the destination register , May be C0, C1...C15.
        <CRm> Additional destination register or source operand register , It is used to distinguish different physical registers with the same number .
              When no additional information is required in the instruction , take C0 Designated as <CRm>, Otherwise, the result of the instruction operation cannot be predicted .
        <opcode_2> Provide additional information , Used to distinguish different physical deposits of a number . When no additional information is specified in the instruction ,
                     Omit <opcode_2> Or specify it as 0, Otherwise, the result of instruction operation is unpredictable .

        cond It's a condition code ,bit20 yes L position ,
         If L=1 It means Load, Read from the outside CPU Nuclear , That is to say MRC Instructions ,
         If L=0 It means Store, That is to say MCR Instructions .[11：8] These four bits are the coprocessor number ,CP15 The number is 15, So it is 4 individual 1.

        CRn yes CP15 Register number ,Rd yes CPU Core register number , Each account 4 position .
         about CP15 Coprocessor , Regulations opcod1 Should be 0,opcode2 and CRm Is an option of the instruction , The meaning depends on different registers .

        
        CP15 Register in :    P180  <<arm_struc_prog>>
        -----------------------------------------------------------------------------
         Register number |     Basic function             |     stay MMU The role of         |     stay PU The role of
        -----------------------------------------------------------------------------    
            0        ID code ( read-only )              ID Coding and cache type         
            1         Control bits (W/R)                     Various control bits
            2         Storage protection and control                  Address translation table base address         Cachability Control bit of
            3         Storage protection and control                  Domain access control bit             Bufferablity Control bits
            4         Storage protection and control                  Retain                      Retain
            5         Storage protection and control                  Memory failure status              Access control bit
            6         Storage protection and control                  Memory failure address              Protection zone control
            7         Cache and write cache              Cache and write cache control
            8         Storage protection and control                 TLB control                      Retain
            9         Cache and write cache              Cache lock
            10         Storage protection and control                 TLB lock                      Retain
            11         Retain
            12         Retain
            13         Process identifier
            14         Retain
            15         It varies from design to design         

        C0:

             register 0,ID Encoding register

             This is a device for returning ID Encoded read-only register

             You can use the opcode2 Set to except 1 Other than to access CP15 Of ID Encoding register R0（CRm At this time, it should be set to 0）. for example ：

            MRC p15,0,Rd,c0,c0,0 ; return ID Register value

             register 0, Cache type register

             This is a read-only register , It contains information about the architecture and size of the cache , This allows the operating system to determine how to perform tasks such as cleaning up the cache
             And locking the cache . all ARMv4T This register is included in cached processors of versions and later , Allow manufacturers of real-time operating systems to produce
             A trial version of their operating system .

             You can use the opcode_2 Set to 1 To visit CP15 Cache type register for R0. Such as ：

            MRC p15,0,Rd,c0,c0,1 ; Returns details about the cache

        C1:    P186
            1. prohibit / Can make MMU And other storage system related functions .
            2. Configure the storage system and ARM How the relevant parts of the processor work .
            
             read :
            mrc p15, 0, r0, c1, 0, 0

             Write
            mcr p15, 0, r0, c1, 0, 0