FPGA - 7 Series FPGA selectio -09- io of advanced logic resources_ FIFO

Preface

Excerpts from this article UG471 Chapter three of , Organize and translate , Used to introduce advanced SelectIO Internal to logical resources IO_FIFO resources .

IO_FIFO summary

7 Series devices in each I/O bank There are shallow layers in both IN_FIFO and OUT_FIFO（ Collectively referred to as IO_FIFO）. Although these IO_FIFO It is specially designed for memory applications , But they can also be used as common resources . For general purposes , All inputs and outputs are routed through interconnections .IO_FIFO The most common use is to connect to external components , As IOLOGIC An extension of （ for example ,ISERDES or IDDR and OSERDES or ODDR）. Because of their universal interconnection capability ,IO_FIFO It can also be used as an additional structure FIFO resources .

Every I/O bank Contains four IO_FIFO, One per byte group IO_FIFO. A byte group is defined as a bank Internal 12 individual I/O. IO_FIFO And I/O Byte group physical alignment . When IO_FIFO Used to connect to IOI Components （ For example, input and output SERDES Elements ） when , This alignment produces the best performance , This is their most common use . however , Whatever its location ,IO_FIFO with FPGA Architecture and others I/O bank Resource interface in . This section focuses on using IO_FIFO And IOI Component interfaces .

For inflow FPGA External data of ,IN_FIFO Can be connected to ILOGIC（ for example ,ISERDESE2、IDDR or IBUF） To receive incoming data and pass it to the structure . For outflow FPGA The data of ,OUT_FIFO Can be connected to OLOGIC（ for example OSERDESE2、ODDR or OBUF） To pass data from the structure to IOB.
IN_FIFO from ILOGIC Block receive 4 Bit data , At the same time, the architecture side reads from the array 4 Bit or 8 Bit data . OUT_FIFO Receive... From the schema 4 Bit or 8 Bit data , and OLOGIC The module reads from the array 4 Bit data .

Every IO_FIFO There is one 768 Bit storage array , Can be arranged as 12 Group 4 Bit data or 10 Group 8 Bit data . One IO_FIFO There are nine entries , Includes an input and output register . Typical IO_FIFO The utility model is used as a parallel cross between two frequency domains I/O Interface buffer （ for example ,BUFR Domain to / come from BUFG or BUFH Domain ） Or as 2:1 The serializer / String unloader , take PHY Separate from the structure , To relax the structural performance requirements .

IO_FIFO It's routine. FIFO The lighter version of , It has similar functions . IO_FIFO The main purpose of is to support I/O Data transmission function . They are not intended to replace built-in FIFO Or based on LUT Of FIFO. IO_FIFO Support standard flag logic 、 Clock and control signals . IO_FIFO It can run in two modes ,4 x 4 Pattern (1:1) or 4 x 8/8 x 4 Pattern (1:2/2:1).

IO_FIFO There is an input register 、 One 7 The entrance is deep FIFO The kernel and an output register , As shown in the figure below . The input and output registers are IO_FIFO Component part , For the complete IO_FIFO Provides an eighth storage location . register 、FIFO The kernel and control signals are treated as a single atomic unit .

IN_FIFO

IN_FIFO Physically related to I/O Byte group alignment to optimize performance . 8 The entrance is deep IN_FIFO Support two operation modes for data transmission ：

• 4 x 4 Pattern —— This mode will FIFO Configured to have 12 individual 4 Bit width data input (D) and 12 individual 4 Bit width data output (Q). D0[3:0] – D9[3:0] Port maps to Q0[3:0] – Q9[3:0] port . D5[7:4] and D6[7:4] Are two additional data input ports D10[3:0] and D11[3:0] And map to Q5[7:4] and Q6[7:4] Additional output ports Q10[3:0] and Q11[3:0]. No other Qn[7:4] port . The following table shows in detail 4 x 4 Schema mapping .

Mapping	Not Used
D0[3:0] → Q0[3:0]	Q0[7:4]
D1[3:0] → Q1[3:0]	Q1[7:4]
D2[3:0] → Q2[3:0]	Q2[7:4]
D3[3:0] → Q3[3:0]	Q3[7:4]
D4[3:0] → Q4[3:0]	Q4[7:4]
D5[3:0] → Q5[3:0]
D6[3:0] → Q6[3:0]
D7[3:0] → Q7[3:0]	Q7[7:4]
D8[3:0] → Q8[3:0]	Q8[7:4]
D9[3:0] → Q9[3:0]	Q9[7:4]
D10[3:0] is D5[7:4] → Q5[7:4]
D11[3:0] is D6[7:4] → Q6[7:4]

• 4 x 8 Pattern —— This mode will FIFO Configured to have 10 individual 4 Bit width data input (D) and 10 individual 8 Bit width data output (Q). stay 4 x 8 In mode ,4 Bit input data is demultiplexed to form 8 Bit output data width . When the output clock frequency is greater than half of the input clock frequency , Usually use 4 x 8 Pattern , So the output data is twice as wide as the input data . The following table shows in detail 4 x 8 Schema mapping .

Mapping	Not Used
D0[3:0] → Q0[7:0]
D1[3:0] → Q1[7:0]
D2[3:0] → Q2[7:0]
D3[3:0] → Q3[7:0]
D4[3:0] → Q4[7:0]
D5[3:0] → Q5[7:0]
D6[3:0] → Q6[7:0]
D7[3:0] → Q7[7:0]
D8[3:0] → Q8[7:0]
D9[3:0] → Q9[7:0]

IN_FIFO The original language

IN_FIFO The primitive is shown in the following figure .

4 x 4 Additional input ports in mode D10 (D5[7:4]) and D11 (D6[7:4]) And output port Q10 (Q5[7:4]) and Q11 (Q5[7:4]).

The following table lists them IN_FIFO Available ports in primitives .

Port Name	Input/output	Description
RDCLK	I	Read the clock . Connect to BUFR、BUFG or BUFH.
WRCLK	I	Write clock . Connect to BUFR、BUFG or BUFH.
RESET	I	Reset , High active . Clear all counters 、 Pointers and data .
D0[3:0] – D9[3:0]	I	4 x 8 Port in mode 10 individual 4 Bit data . stay 4 x 4 The ports in mode have 12 individual 4 Bit data . If used for external interfaces , Then connect to ILOGIC.
D5[7:4], D6[7:4]	I	port D10 and D11 Supplementary data in . Only used for 4 x 4 Pattern . The data on the port appears on the corresponding output port Q5[7:4] and Q6[7:4] On .
RDEN	I	Reading enable
WREN	I	Write enable
Q0[7:0] – Q9[7:0]	O	10 individual 4 x 8 Mode 8 Bit data output bus , or 10 individual 4 x 4 Mode 4 Bit data output bus . If used for external interfaces , Then connect to the structure .
Q5[7:4], Q6[7:4]	O	Supplementary data output port Q10 and Q11. Only used for 4x4 Pattern . The data on these ports comes from the corresponding input port D5[7:4] and D6[7:4].
EMPTY	O	Empty flag . And RDCLK Sync .
FULL	O	Full sign . Synchronize to WRCLK.
ALMOSTEMPTY	O	Programmable level null flag . And RDCLK Sync .
ALMOSTFULL	O	Programmable level full flag . Synchronize to WRCLK.

ALMOSTEMPTY、ALMOSTFULL The corresponding properties can be set to values 1 or 2. therefore , At least one or two reads or writes occur after the flag is set . because FIFO The asynchronous nature of , There may be one or two additional reads or writes , Increase the total number of reads or writes to three to four .

OUT_FIFO

OUT_FIFO And IN_FIFO In the same place , And physically with I/O Byte group alignment to optimize performance . 8 The entrance is deep OUT_FIFO Support two operation modes for data transmission ：

• 4 x 4 Pattern —— This mode will FIFO Configured to have 12 individual 4 Bit width data input (D) and 12 individual 4 Bit width data output (Q). D0[3:0] – D9[3:0] Port maps to Q0[3:0] – Q9[3:0] port . D5[7:4] and D6[7:4] Are two additional data input ports , Used as a D10 and D11, And map to Q5[7:4] and Q6[7:4] Output port . other D[7:4] Port not used . The following table shows in detail 4 x 4 Schema mapping .

Mapping	Not Used
D0[3:0] → Q0[3:0]	Q0[7:4]
D1[3:0] → Q1[3:0]	Q1[7:4]
D2[3:0] → Q2[3:0]	Q2[7:4]
D3[3:0] → Q3[3:0]	Q3[7:4]
D4[3:0] → Q4[3:0]	Q4[7:4]
D5[3:0] → Q4[3:0]
D6[3:0] → Q6[3:0]
D7[3:0] → Q7[3:0]	Q7[7:4]
D8[3:0] → Q8[3:0]	Q8[7:4]
D9[3:0] → Q9[3:0]	Q9[7:4]
D10[7:4] is D5[7:4] → Q5[7:4]
D11[7:4] is D6[7:4] → Q6[7:4]

• 8 x 4 Pattern —— This mode will FIFO Configured to have 10 individual 8 Bit width data input (D) and 10 individual 4 Bit width data output (Q). stay 8 x 4 In mode , In the output data path 2:1 The multiplexer will 8 Bit input data is serialized to 4 Bit output data width . 4 x 8 The mode is generally when the output clock frequency is twice the input clock frequency , Therefore, it is used when the output data is half the width of the input data . The following table shows in detail 8 x 4 Schema mapping .

Mapping	Not Used
D0[7:0] → Q0[3:0]
D1[7:0] → Q1[3:0]
D2[7:0] → Q2[3:0]
D3[7:0] → Q3[3:0]
D4[7:0] → Q4[3:0]
D5[7:0] → Q5[3:0]
D6[7:0] → Q6[3:0]
D7[7:0] → Q7[3:0]
D8[7:0] → Q8[3:0]
D9[7:0] → Q9[3:0]

Both models support FULL、EMPTY、ALMOSTFULL and ALMOSTEMPTY sign .

OUT_FIFO The original language

OUT_FIFO The primitive is shown in the following figure .

Additional input ports D10 (D5[7:4]) and D11 (D6[7:4]) And output port Q10 (Q5[7:4]) and Q11 (Q5[7:4]) stay 4 x 4 Pattern .

Port Name	Input/output	Description
RDCLK	I	Read the clock . Connect to BUFR、BUFG or BUFH.
WRCLK	I	Write clock . Connect to BUFR、BUFG or BUFH.
RESET	I	Reset , High active . Clear all counters 、 Pointers and data .
D0[3:0] – D9[3:0]	I	4 x 8 Port in mode 10 individual 4 Bit data . stay 4 x 4 The ports in mode have 12 individual 4 Bit data . If used for external interfaces , Then connect to ILOGIC.
D5[7:4], D6[7:4]	I	port D10 and D11 Supplementary data in . Only used for 4 x 4 Pattern . The data on the port appears on the corresponding output port Q5[7:4] and Q6[7:4] On .
RDEN	I	Reading enable
WREN	I	Write enable
Q0[7:0] – Q9[7:0]	O	10 individual 4 x 8 Mode 8 Bit data output bus , or 10 individual 4 x 4 Mode 4 Bit data output bus . If used for external interfaces , Then connect to the structure .
Q5[7:4], Q6[7:4]	O	Supplementary data output port Q10 and Q11. Only used for 4x4 Pattern . The data on these ports comes from the corresponding input port D5[7:4] and D6[7:4].
EMPTY	O	Empty flag . And RDCLK Sync .
FULL	O	Full sign . Synchronize to WRCLK.
ALMOSTEMPTY	O	Programmable level null flag . And RDCLK Sync .
ALMOSTFULL	O	Programmable level full flag . Synchronize to WRCLK.

ALMOSTEMPTY、ALMOSTFULL The corresponding properties can be set to values 1 or 2. therefore , At least one or two reads or writes occur after the flag is set . because FIFO The asynchronous nature of , There may be one or two additional reads or writes , Increase the total number of reads or writes to three to four .

Reset IO_FIFO

One IO_FIFO There is an asynchronous reset , It is internally resynchronized with the read and write clock fields . To ensure correct reset , In the writing IO_FIFO Before , Must be RESET Set to high level for at least four RDCLK or WRCLK cycle , Whichever is slower . When RESET When asserted ,RDEN and WREN Must be kept low .

IO_FIFO It shall be kept in reset state , Until both the write and read clocks are present and stable . Similarly , If the read or write clock is not available after configuration ,IO_FIFO It must be reset after the effective clock is set as described above .

EMPTY and FULL sign

FULL The flag is set to high level , Express FIFO The kernel and input registers are full . The state of the output register is ignored .EMPTY Flag indicates the status of the data in the output register . When EMPTY The flag is set to high level , Invalid data in output register .ALMOST EMPTY and ALMOST FULL sign ALMOSTEMPTY and ALMOSTFULL The logo provides IO_FIFO Early indications of approaching their limits . These flags can be configured to be displayed in IO_FIFO One or two cycles are asserted before the full or empty state is reached . value 1 Indicates that there is only one word left to read or write . value 2 Indicates that there are two more words to read or write .

because IO_FIFO And internal synchronization , Signs may be too pessimistic . During a read operation , The stored data may be larger than ALMOSTEMPTY Flag output 1 or 2 There are many indications . During a write operation , The space available for writing may be larger than ALMOSTFULL Flag output 1 or 2 There are many indications .

ALMOSTEMPTY and ALMOSTFULL sign

Not necessarily with FULL and EMPTY Flag overlap . Can be in EMPTY Let before asserting ALMOSTEMPTY Assert and cancel assert . If WRCLK Than RDCLK More than twice as fast , That's what happens . The following table summarizes all applicable IO_FIFO attribute .

Attribute	Value	Default Value	Description
ARRAY_MODE (IN_FIFO)	String: ARRAY_MODE_4_X_8 ARRAY_MODE_4_X_4	ARRAY_MODE_4_X_8	Define each port 4 Input bits and 4 Or 8 Output bits .
ARRAY_MODE (OUT_FIFO)	String: ARRAY_MODE_8_X_4 ARRAY_MODE_4_X_4	ARRAY_MODE_8_X_4	Define each port 4 or 8 Input bits and 4 Output bits .
ALMOST_EMPTY_VALUE	Integer: 1 or 2	1
ALMOST_FULL_VALUE	Integer: 1 or 2	1
OUTPUT_DISABLE	Boolean: TRUE or FALSE	FALSE	OUT_FIFO： When RD_EN Low power level , Output Disable drive Qx The output is high level .

reference

1. UG471