Principles of microcomputer Chapter 5 notes arrangement

ARM characteristic

• Fixed length opcode , Simplify decoding , Convenient for assembly line design
• Multiple general purpose registers , Instructions are not limited to a particular register
• The operand address is specified by a register or instruction , The address is automatically increased or decreased
• Each data instruction can control arithmetic logic unit and displacer
• Multi register load store instruction
• All instructions are conditionally executable
• Support Thumb Instruction set

ARM7

Have MPU, Divide the memory space into different domains , Implement privilege level access control

Have MMU, Support virtual memory

Cortex-A

High performance processors for mobile computing, etc

Cortex-R

For high-performance real-time applications

Cortex-M

Focus on low cost , Low power applications

Corte-M3/M4

belt SysTick, for OS Provide timed interrupts

With two stack pointers

• OS Use the main stack pointer with exceptions MSP

• User processes use process stack pointers PSP

Support independent privileges / Non privileged access level

CPU

32 position RISC, Level three （ address-of , decoding , perform ） Assembly line , Harvard structure

NVIC

6 A priority

FPU

Bus switching matrix

For all kinds of memory , On chip and off chip devices and debugging components provide multiple buses , Data and instructions can be transmitted in parallel on different buses .

With write buffer

Matching MPU

Debug components

Debugging refers to reading through the debugging interface / Modify the internal registers of the processor / Memory contents , Issue debug command

Tracing refers to collecting information during operation without stopping the normal operation of the processor

Memory management

• 4GB Linear address space
• Determined memory mapping relationship
• Support size end
• Bit band operation
• With write cache
• Optional MPU
• Misaligned transfer

Memory mapping

• Code access area
• Data storage area
• Peripheral port area
• Processor internal control debug part area

Bus system

• I-Code Bus

  AHB-Lite32 A bus , visit CODE District , Address is taken in words , Yes 16 position Thumb Instructions , Take two at a time

• D-Code Bus

  AHB-Lite32 A bus , The access area is the same as above , Take the data

The two buses are physically independent , There are arbitrators between each other ,D-Code first , To avoid conflicts, code data can be stored separately . Code exists flash in , Data exists SRAM in

• System Bus

  32 position APB Bus , Sometimes it becomes AHB Bus

• APB/PPB Bus

  32 position APB Bus , Responsible for external private peripherals

NVIC

Include 240 External interrupts , A non maskable interrupt NMI Multiple system exceptions, including 0~15 Assigned to system exception （ Actually used 11 individual , Include NMI）

among

• Except reset &NMI, Can be shielded
• Except reset ,NMI, Hardware error , Can be prohibited separately / Can make
• Except reset ,NMI, Hardware error , Fixed high priority , The interruption has 256 Level priority , most 128 Preemptive priority
• Automatically give the handler entry when responding
• Interrupts and various exceptions can be triggered by software
• Save automatically / Restore the scene
• Optional wake-up interrupt controller

SysTick

Kernel devices , contain 24 position , Periodically trigger interrupts ,

Interrupt vector table

Service program entry , Each entrance 4 byte

The default location is at the beginning of the storage space

Interrupt vector table can change position , It is called relocation

Cortex-M3/M4 Programming model

Support 16 position 32 Bits coexist Thumb-2 technology , No, ARM and Thunmb Points

Operation state

• Thumb

• debugging

  Debug state down tester read / write register

  The two state adjustment testers can access the system memory

There are two ways to enter the debug state

• The debugger initiates a pause request
• The debug component in the processor generates a debug state

Operation mode

• Processing mode

  Execute interrupt service procedure

• Thread mode

Access level

• Processing mode

  At the privilege level , Access to all resources

• Thread mode

  • Privileged threads
  • Unprivileged threads

  It can be written in privileged thread mode CONTROL Register switch to non privileged mode , Non privileged mode does not work , Only with exceptions

  Privilege / Non privileged differences

  • A few instructions can only be executed in privileged mode, otherwise exceptions will occur
  • Non privileged access to most kernels
  • Non privileged cannot access part MPU Area

Thread mode is optional PSP/MSP, Processing mode can only use MSP, This separates the application stack from the system stack , More reliable .

The system is in privileged thread mode after reset

General register

common 16 individual ,13 A for 32 Bit Universal , The rest are stack pointers MSP/PSP, Link Register LR And program counter PC

R0-R12 For general purpose ,R0-R7 Weigh the low order , Other high positions

many 16 position Thumb Only low order registers can be accessed , The high register is used for 32 Bit instruction and minority 16 Bit instruction

among R0_{R3 For parameter passing ,R4}R11 For local variables ,R12 Calling intermediate registers for subroutines

R13 Stack pointer

Only one of the dual stacks is visible ,MSP By default

After reset PSP Undefined ,MSP In the first word of storage space

MSP and PSP The last two digits must be 00, Unable to write

R14 Link Register

Used for function return address

The end of the return address must be 0, Can be written as 1 The logo is in Thumb state

R15 Program counter

Can read but write , The read instruction returns the current value plus 4

The lowest is 0, When writing, the lowest bit is 1, Otherwise, it will be deemed as an attempt to transfer to ARM, High level programming language is set automatically 1

Special register

Used to identify processor status , Processor operation status and set interrupt mask

High level languages don't need

• Program status register

  • CPSR

    Current program status

  • SPSR

    Used to save... During exception handling CPSR state

    Break nesting with stack save

  After use PSR Instead of CPSR, Cancel SPSR, Used in case of abnormality LR preservation PSR

  PSR contain

  • APSR

    Application status register

  • EPSR

    Execute program status register

  • IPSR

    Interrupt program status register

• Priority based interrupt masking

  • PRIMASK

    Only one person works

    if 1, Shield removal reset ,NMI, Hardware error external interrupt

    After completion, it is necessary to clear 0

  • FAULMASK

    The same person works

    if 1, Hardware errors are also masked , Used to handle hardware errors , Automatically clear after processing 0

  • BASEPRI

    Interrupt can be masked by value

    8 Bit scalable , Depending on the manufacturer

    Mask interrupts with numbers greater than the register value

• CONTROL

  • nPRIV

    Set the privileged access level in thread mode

    0 For privilege ,1 For non privileged

  • SPSEL

    Used to switch stack pointer types

    by 0 Only MSP,1 by PSP

    Processing mode reset defaults to 0

  • FPCA

    Handle FPU

• SCB System control block

  Multi register data structure

Stack structure

be used for

• Save the next instruction address when responding to an interrupt , Status register contents
• Save the scene , Register used
• It is used to transfer parameters of main program and subroutine
• local variable

Divided into incremental / Reduce stack , The incremental stack points to the high address growth

full / Empty stack , The full stack top pointer points to the top element , The empty stack points to the next

Cortex-M Full decrement

Cortex-M The storage system

Memory mapping

common 4G

Area	purpose
00000000~1FFFFFFF	512M,Icode Instructions ,Dcode data , Release the program code , Interrupt vector table , data
20000000~3FFFFFFF	512M, On film SRAM, Data or code , The first 1M Support bit segment operation
40000000~5FFFFFFF	512M, Peripherals on the film , The system bus , The first 1M Bit segment
60000000~9FFFFFFF	Two 512M, Off chip storage
A0000000~DFFFFFFF	Off chip peripherals / Other storage
E0000000~FFFFFFFF	System . Internal private peripheral bus E0000000E003FFFF, be used for NVIC,SysTick,MPU, Most are at the privilege level . External private peripheral bus E0040000E00FFFFF, Other commissioning , Privilege . Customize E0100000~FFFFFFFF

Programs are usually placed in the code area , Otherwise, additional cycles are required , The program is not allowed to execute in peripheral area and system storage area

Connect memory and peripherals

The main use of AHB Lite, Applicable to single master control equipment , Bus matrix arbitration is required

Private peripherals use APB

Bit segment operation

Or bit band

A memory operation accesses one bit , Each word in the bit segment area is mapped to a bit segment alias area , A bit segment alias region corresponds to a bit of a word in the bit segment region

The bit segment area is generally accessible , It can also be accessed through bit segment aliases

Operation atomicity can be guaranteed

Memory access

attribute

• Bufferable
• Caching
• Executable
• Can share

Bus interface writeable buffer

Multiprocessors need to share attributes to ensure consistency across cache units

Exclusive access

Use semaphores

bootloader

Cortex-M exception handling

Abnormal state

• Inactive state

• Pending state

  A service request is pending

• active

  Being processed

• Activate and suspend state

  When the same exception source is being processed, it generates

Priority register

3~8 position , Priority is given to the high order

Interrupt priority grouping

Can be set up SCB Prioritize groups

Abnormal flow

• Accept the request

  If meet

  • The processor runs
  • Exception enable
  • Exception priority is higher than current
  • Exceptions are not masked

• Entry exception

  • Multiple registers and return addresses are stacked
  • Take the exception vector
  • Get the exception handler instruction
  • to update NVIC Registers and kernel registers （PSR,LR,PC）

• Perform exception handling

• Exception return

Set interrupt suspend and clear interrupt suspend

You need two registers