Embedded hardware development tutorial -- Xilinx vivado HLS case (process description)

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This paper mainly introduces HLS How to use the case , Applicable development environment ：Windows 7/10 64bit、Xilinx Vivado 2017.4、Xilinx Vivado HLS 2017.4、Xilinx SDK 2017.4.

Xilinx Vivado HLS（High-Level Synthesis, High level synthesis ） Tool support will C、C++ And so on , At the same time, support based on OpenCL And so on Xilinx Programmable logic device development , It can accelerate the process of algorithm development , Shorten time to market .

This case uses the technology of chuanglong TLZ7x-EasyEVM-S Development board , It is based on Xilinx Zynq-7000 series XC7Z010/XC7Z020 Heterogeneous multi-core processor with high performance and low power consumption SoC Evaluation board , Processor Integration PS End binuclear ARM Cortex-A9 + PL End Artix-7 framework 28nm Programmable logic resources , The evaluation board is composed of core board and evaluation bottom board . The core board has been professionally PCB Layout And high and low temperature tests to verify , Stable and reliable , It can meet various industrial application environments .

TLZ7x-EasyEVM-S Evaluation board

TLZ7x-EasyEVM-S Evaluation board evaluation board interface resources are rich , Leading out Gigabit Ethernet port 、 dual CAMERA、USB、Micro SD、CAN、UART Such as the interface , Support LCD Display expansion and Qt GUI development , It is convenient for rapid product scheme evaluation and technical pre research .

HLS The basic development process is as follows ：

1. HLS The project is newly built / Project import
2. Compilation and simulation
3. comprehensive
4. IP Nuclear packaging
5. IP Nuclear testing

HLS The case catalogue is described in detail in the following table .

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Catalog	Catalog	file / Catalog	explain
hls_ip_demo	bin or hw/bin	xxx_xc7z010.bin/xxx_xc7z010.bit	xc7z010 PL End IP Nuclear test executable
		xxx_xc7z020.bin/xxx_xc7z020.bit	xc7z020 PL End IP Nuclear test executable
	project or hw/project	xxx_xc7z010	xc7z010 PL End IP Nuclear testing Vivado engineering
		xxx_xc7z020	xc7z020 PL End IP Nuclear testing Vivado engineering
	sw	bin	PS End IP Core test bare metal executable
		project	PS End IP Nuclear testing bare metal engineering
vivado_hls	ip_package	xxx.zip	IP nucleus
	project	solution	Simulation scheme
		src	HLS Engineering source
		test_bench	HLS Engineering simulation program or test file
		vivado_hls.app	HLS Engineering documents

HLS For detailed development instructions, please refer to the following documents .

1. ug871-vivado-high-level-synthesis-tutorial.pdf
2. ug902-vivado-high-level-synthesis.pdf

HLS Development process description

This chapter is based on product data “4- Software data \Demo\FPGA-HLS-demos\” In the catalog led_flash Take the case as an example , demonstration HLS Development process . The function of this case is by PL End control evaluation backplane LED2 Flashing .

Before that , Please copy the corresponding case directory to Windows In the non Chinese path .

remarks ：Windows The path has a length limit , Too long path will lead to an error in opening the project .

Before doing the following in this article , Please install the debugging tool according to the debugging document Xilinx Vivado Development kit . By default, this article uses the TL-DLC10 Downloader for operation demonstration .

HLS Project import

Double click the following icon on the desktop to open Xilinx Vivado HLS 2017.4, And click... In the pop-up interface “Open Project” Choose a case “vivado_hls\project\” Catalog , And then click “ determine ” Import HLS engineering .

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You can also build HLS engineering , And use C/C++ And so on .

Compilation and simulation

The emulator is located in Test Bench Under the table of contents , Used to verify Source In the catalog HLS Engineering source .

Import HLS After the project , Click on (Run C Simulation) Compile and simulate .

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The following interface will pop up , Check “Launch Debugger”, And click the OK.

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After compilation , It can run at full speed or in one step .

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comprehensive

This section demonstrates C/C++ And so on RTL Design , And generate a comprehensive report .

Click the upper right corner of the interface Synthesis Back to the engineering interface , Then click to start synthesis .

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After the integration , The report file will open automatically .

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Through the report file, we can see the design time delay 、 Information such as resource occupancy .

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IP Nuclear packaging

After the integration , Click generation IP nucleus .

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After completion of operation , It will be in the case “vivado_hls\project\solution1\impl\ip\” Generate under directory IP nucleus .

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IP Nuclear testing

Enter the case “hls_ip_demo\project\” or “hls_ip_demo\hw\project\” Corresponding platform PL End IP Nuclear testing Vivado Project directory , double-click .xpr File open project , The project has added to be tested by default IP nucleus .

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To import IP nucleus , Please refer to the following steps .

1. Please click on “IP Catalog -> User Repository -> Add IP to Repository…”, Select... In the pop-up interface IP Click after checking OK.

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1. Right click “User Repository” Then click “Refresh Repository”, You can see the added IP nucleus .

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1. To add Vivado Self contained IP nucleus , Click on “Open Block Design”, Click... In the pop-up interface , And choose what you want IP The nuclear power will lead it into Engineering .

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Click on Vivado On the left side of the interface “Generate Bitstream” Options , Click... In the pop-up interface OK Conduct PL End IP Nuclear testing Vivado Engineering compilation .

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After compilation , Will be in Engineering “led_flash.runs\impl_1\” Generate under directory .bit and .bin Format executable .

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Reference resources PL End case development manual description loading PL End .bit Format executable , You can see the evaluation of the floor LED2 Flashing .