Introduction to MgO 256gb NAND flash chip

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General overview

The chip is a typical large capacity NAND Flash Storage particles , Support Open NAND Flash Interface (ONFI) 2.1 Interface standard of , use ONFI NANDFlash Operating agreement for . The chip uses Multiple-level Cell （MLC） technology , Depending on the capacity , A chip is internally packaged with multiple DIE（LUN）, Every DIE By two Plane constitute , One Plane Can be divided into 2048 individual Block, Every Block from 256 Page composition , The size of a page is 8KB+448B The organizational structure of .

In terms of performance , One Page The read delay of the page is 50us about , Page programming time is 900us, Block erasure takes up to 3ms. Each block has a nominal erase life of 5000 Time .

Chip interface and signal

MgO's chip supports synchronous and asynchronous interface modes . In asynchronous interface mode , use 5 A control signal , Respectively #CE,CLE,ALE,#WE and #RE, in addition #WP It is used to control the write protection of the chip ,R/#B Used to detect the current state of the chip . In synchronous operation mode ,#WR The pin is the clock input signal ,#RE The signal is the reading / writing direction indication signal .

NAND Flash The interface signal of is specifically defined as follows ：

One NAND Flash A physical chip can be composed of multiple DIE（ Or call it LUN） Unit composition of , Every DIE There will be a set of independent control signal lines mentioned above . One DIE There will be several Plane, Every Plane There are many Block Unit composition , One Block Cell is the smallest erasure unit , And there are many Page Page composition , The smallest unit written each time is one Page page . For smaller chips , Chip manufacturers will only package one DIE, Every DIE The internal structure of is shown in the figure below ：

For magnesium 512Gb chip , One DIE Internally, there are two Plane, Through a set of control signal lines and registers to control the internal two Plane Concurrent work . It is worth mentioning that , Multiple DIE（LUN） May share a set of control signal lines , therefore , Physically multiple DIE It's going to be packaged as a Target. It should be noted that , The same Target Inside DIE Although the physical signal lines are shared , But the registers are independent of each other . therefore , Structurally , One NAND Flash The internal architecture of can consist of only one DIE（LUN） constitute , As shown in the figure below ：

It is also possible to integrate multiple in one chip DIE（LUN）, Every DIE Have a set of independent physical signal lines , As shown in the figure below ：

In high-density packaging , There are not so many physical signal lines , So the same Target Multiple... Will be integrated in DIE（LUN）, If the figure below shows ：

No matter how to package , Every DIE（LUN） The basic structure of is the same .

NAND Flash Storage unit

NAND Flash In a DIE（LUN） A storage unit in a usually consists of multiple Plane constitute , Its structure is as follows ：

The one shown above Page Page size is 8KB, in consideration of spare area Of 448 Byte space , Therefore need 14 Bit address to access a page page , That is, the lowest address signal 14 Bit is in page address . One block Inside the block there are 256 individual page page , need 8 Bit address （Page address,PA） Information to access a block Differences within the block page page . One Plane It's inside 2048 individual block block , need 11 position （Block address,BA） To visit a Plane Different in block block . One DIE（LUN） in 2 individual Plane, An address bit is required to access a DIE Different in Plane. therefore ,40 The definition of bit address information is shown in the following table ：

CA0~CA13 Access address information for intra page offset ,PA0~PA7 For page address information ,BA8 by DIE Medium Plane Select the address bit ,BA9~BA19 by DIE Block address information in , in addition ,LA0 For one Target Medium DIE（LUN） Select the address bit , In the NANDFlash In chip , One Target You can integrate 2 individual DIE.

At every Plane There are two registers in each cell ： One for cache register ; For another data register .Cache The function of registers is to cache NAND Flash Data input by the controller , and data The function of registers is to improve the performance of data reading and writing , Operation between data transfer and data loading . In the process of data reading and data writing , Both provide pipeline concurrent operation mode , These models take full advantage of this data register .

Read / write operation sequence

Magnesian NAND Flash The chip provides two modes of operation , One is asynchronous operation mode ; The other is synchronous operation mode . Asynchronous operation is a traditional interface mode ,NAND Flash And the controller are in two clock domains , All signals need to be synchronized during data transmission , So the performance is poor . The reference clock for synchronous operation is provided externally ,NAND Flash In the same clock domain as the controller , High read / write performance can be achieved .

Asynchronous operations

The asynchronous operation mode is very suitable for the controller such as single chip microcomputer to operate it , No special NAND Flash controller , Common bus operation can be used to NAND Flash Carry out control operation . The sequence of asynchronous data write operations is shown in the following figure ：

stay #WE Driven by the signal ,DQ Input the corresponding data on the bus , And in #WE After the rising edge of the signal, it is necessary to keep tDH Time . stay #WE Driven by the rising edge of the signal ,DQ The data on the bus is latched to NAND Flash In the data register of .

stay RDY When the signal is high , Instructions can be from NAND Flash Read data from the specified location , The sequence of read operations is shown in the following figure ：

Reading signals #RE Driven by the falling edge of , Data from NAND Flash To the data bus DQ On .NAND Flash The controller can be used in #RE The rising edge of the signal samples the data bus DQ The data on the . When NAND Flash When the signal reading frequency given by the controller is fast , adopt #RE When the rising edge signal fails to properly sample the data on the data bus , You can go to the next #RE The falling edge of the signal samples the output data on the bus . As shown in the figure below ：

therefore , During asynchronous bus operation , You need to consider #RE Read signal frequency and tRC Time relationship between . Through this time relationship to determine the specific read data sampling method .

Synchronous operation

Synchronous operation is a high-speed interface , and DDR Memory interfaces are similar , The data transmission efficiency can be improved by sampling the upper and lower edges at the same time . In synchronous mode , The clock signal requires an external continuous input ,NAND Flash By controlling ALE、CLE、#CE、W/#R、DQS Signal to control the input and output of data . The data input sequence in the synchronous mode is shown in the following figure ：

DQS The signal is from NAND Flash Controller drive , And in the same frequency and phase as the clock signal . stay CLK The rising and falling edges of the clock signal lock the data on the bus to NAND Flash Internal deposit . In order to be able to make NAND Flash stay DQS The rising and falling edges of are sampled to the data on the bus , Before changing along the ,NAND Flash The controller needs to be on the bus DQ Data ready to be written on .

When RDY When the signal is high , Show that you can start from NAND Flash Output data in . During the read operation , data bus DQ、 Bus indication signal DQS Need by NAND Flash control , The controller needs to release control of these signal lines . The operation sequence of data read bus is shown in the figure below ：

The bus data latch signal can be found DQS And clock signals CLK Same frequency , But there will be some differences , such NAND Flash The controller can be controlled by CLK The double edge change of the clock signal samples the data on the bus , Thus, it can read correctly NAND Flash Data in .

NAND Flash Operation command

NAND Flash The operation of is accomplished by a series of commands . The operation commands of the MgO chip are defined as follows ：

The orders are divided into 9 Categories: , Including reset operation 、 Identify operations 、 Configuration operation 、 State operation 、 Address operation 、 Read operations 、 Write （ Programming ） operation 、 Erase and writeback operations . stay NAND Flash The controller software needs to encapsulate these lowest level commands into NAND Flash Operation Library .

Read command

For read operations ,NAND Flash Provides multiple modes . Ordinary page reading operations are inefficient , When initiating page reading, you need to input specific commands and address information , Then output the data , The specific operation sequence is shown in the figure below ：

After entering the command and address information ,RDY The signal goes low ,NAND Flash You need to wait a while before you can output data , When the data is ready , When you can output ,RDY The signal goes high .NAND Flash In this process, it is necessary to continuously detect RDY The signal , When the signal changes from low to high , You can output data synchronously or asynchronously .

stay NAND Flash Internal , There is one data cache register , Through this register, the data reading operation can be divided into two stages ： One is from page cache Register to NAND Flash The controller transmits data ; The other is from NAND Flash To the data Register load data . These two operations can be pipelined , command 0x31 It is used to implement this pipeline concurrent operation . In order to improve the efficiency of data output , On the basis of normal page reading , adopt 0x31 Commands can be used in data from page cache Output from NAND Flash To the data cache Load new data . This concurrency pattern falls into two categories ： One is sequential reading , The other is random reading , There are differences in operation timing . The following figure shows the sequence of concurrent sequential reads ：

The data at the specified address is from page cache At the same time ,NAND Flash The next page of data will be loaded into data In the register , So when NAND Flash The controller has read the specified page After the data in , The data of the next page has been loaded successfully . Through this pipeline mechanism , Improve reading performance .

In addition to pipeline concurrency sequence page Out of page , You can also put random page Page for concurrent pipeline reading , As shown in the figure below ：

After the page read command is sent , When the data is loaded into page cache after ,RDY The signal is set from low to high . Then enter another page address , And pipeline loading command 0x31. stay page cache While the data in is outputted to the outside ,NAND Flash The data in is output to data In the register . In this way, two discrete data can be read concurrently page Page data .

For concurrent reading of two plane Data in ,NAND Flash Also provided 0x00-0x32 Control command , With this command, multiple plane Concurrent loading of data , from NAND Flash Load into the corresponding page cache in .

Write （ Programming ） command

Normal write commands allow NAND Flash The controller writes data to NAND Flash Medium page cache register , And take the data from page cache Write to... In the register NAND Flash In the medium . A common page programming sequence is shown in the following figure ：

The process can be divided into three steps ： The first step is to input the control command 、 Operation address information ; Step 2 input the data to be written to page cache; Step 3 start programming , take page cache The data in the register is written to NAND Flash medium .

If each write operation goes through the above process , Then the write delay will become very long . To improve page write performance ,NAND Flash Pipeline concurrency mode is provided , This model makes full use of data register . The command used is 0x80-0x15, The sequence is shown in the figure below ：

In this mode , Under the control of address and command , Data is first written to page cache In the register . When 0x15 After the control command is sent ,page cache The data in the register will be copied to data In the register . While the copy is in progress RDY The signal is set low , When the copy is complete ,RDY The signal goes high .NAND Flash In this case, the controller can input the data of the next page , In the process of data input on the next page ,NAND Flash Will be concurrent with data The data in the register is written to the specified medium . Thus, the pipeline concurrency between the controller input and the specific programming operation can be achieved , Improved page Throughput of page write operations .

When you need to end pipelining , After the last page of data is written , write in 0x10 Command is enough . The specific sequence operation is shown in the figure below ：

For concurrent programming two Plane Data pages in ,NAND Flash Provides 0x80-0x11 command . This command allows you to write data directly to multiple Plane Medium page cache In the register , So as to realize multiple Plane The data pages in are written concurrently .

Erase operation command

Erasure is a very time-consuming operation , about NAND Flash for , The smallest erasure unit is block block . When a block needs to be erased , You need to input the address of the block and the corresponding control command , The specific timing is shown in the figure below ：

In the process of erasing ,RDY The signal will be set low , At this point the DIE Normal read and write operations will not be possible . therefore , Although different Plane Have different register groups between , But because the physical signal lines are shared , therefore , Once a Plane Medium block Entered the erase state , So the whole DIE The read and write operations of will be affected .

COPYBACK command

stay wear-leveling operation , perhaps garbage collecting When , It is usually necessary to put a page Copy the data in the page to another page page , And that's where it comes in COPYBACK The function of . This command can convert a page The data in the page is loaded into the register , Then write directly to the specified other page Page .

In actual operation , in consideration of NAND Flash The data in may have been corrupted ,NAND Flash Generally, it is recommended that the controller be in the process of data copying , Verify the migrated data . So NAND Flash Provides COPYBACK READ Control operation process , As shown in the figure below ：

COPYBACK READ After the command is executed , The data will be entered into NANDFlash controller , In the controller ECC The decoder verifies the data , If the data goes wrong , So in COPYBACK WRITE The correct data can be written to NAND Flash in , In the process, you can use CHANGE WRITE COLUME Realize to page Random writes to pages . The timing is shown in the figure below ：

When the updated data is written to Page cache After register , Start page programming , complete COPYBACK operation .

（ Wuzhongjie , The way of storage ）

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