FPGA notes -- implementation of FPGA floating point operation

One 、IEEE-754 standard

        IEEE-754 Standard numerical representations include : Floating point numbers , Special values ( zero , infinity , Non standard value ,nan), Single precision 、 Double precision 、 Floating point numbers in single precision extended format .

(1) Floating point format . stay IEEE-754 In the standard , All floating-point numbers are represented by binary templates :

IEEE-754 Format

 

among ,S The field represents the sign bit ,E The field represents the exponent ,M Fields represent mantissa ( A part or fraction of a logarithm ). For standard floating point numbers , The default always exists 1 An implied boot bit “1”. for example , Binary number 1.0011 Or decimal numbers 1.1875 use IEEE-754 When expressed in standard format, its M A value of the domain 0011, Do not save the implied pilot bit in the identification format “1”. For nonstandard floating point numbers , The boot bit can be “1” or “0”. For zero , Infinity and nan, M The field has no implied leading bits “1” Or there is no explicit boot bit .

(2) Single-precision floating-point . Single precision floating point numbers use 32 Bit binary number means , The highest of them ( Bit[31], MSB) Symbol bit , namely S Domain ; Bit[30:23] by E Domain , this 8 Bit data represents the index ; Lowest 23 position (Bit[22:0], LSB ) by M Domain , Used to represent the fractional part of a floating-point number .

(3) Double precision floating point . Double precision floating point numbers use 64 Bit binary number means , The highest of them ( Bit[63], MSB) Symbol bit , namely S Domain ; Bit[62:52] by E Domain , this 11 Bitwise index ; Lowest 52 position (Bit[51:0], LSB) by M Domain , Used to represent the fractional part of a floating-point number .

So it represents a floating point number y The values are as follows

                                                                             

Two 、 The addition and subtraction of floating-point numbers

        The implementation of floating-point addition operation includes the following steps: symbol judgment 、: Antithetic order 、 Mantissa addition and subtraction operation 、 normalized 、 Rounding operation 、 Overflow judgment . The concrete implementation usually normalizes 、 Rounding operation 、 Overflow judgment is implemented as a step . The format of floating point numbers can obviously be divided into two parts , That is, the absolute value of symbols and data . If the symbols are the same, the symbols cannot be added to the absolute values ; If the symbols are different, the size of the two absolute values must be compared, and then the two absolute values are calculated by difference . When the symbol is different, the symbol that first judges and , Obviously, if the order of two floating-point numbers is different, the sign of the sum should be the same as the operand with large order ; If the order is different, continue to compare the opposite order operation. First, compare the order of the two floating-point numbers . Then we need two pairs of orders . The principle of order is small order to large order , The advantage of small order to large order is , When the small order is different from the large order , Just remove the lower part of the mantissa of the small order . The addition flow chart is shown in the figure below

Add / Subtraction process

 

3、 ... and 、 Multiplication of floating point numbers

The multiplication of floating-point numbers is relatively simple , You only need to XOR the sign bits of the two operands , Then sum the order code part 、 Product the mantissa . At the same time, it is necessary to check whether the result of operand operation has overflow problem . The multiplication process is shown in the following figure :

ride / Division process

 

Four 、 Use Altera Of IP The kernel implements floating-point operations

        The following figure for Altera Floating point addition operation provided IP Core setting interface .

IP nucleus

IP The core is set to 64 Bit input and output 、 Delay 14 Clock cycle output results 、 Select speed optimization 、 Can make ‘ Add 、 reduce ’ Dynamic switching function . See the following table for module function pins

Module pin function

Signal name	Signal direction	explain
dataa	I	The data input conforms to IEEE-754 standard
datab	I	The data input conforms to IEEE-754 standard
add_sub	I	Dynamic switching of addition and subtraction function , High level performs adding operation
clk	I	The system clock
result	O	Operation output
NaN	O	NaN Abnormal output
overflow	O	overflow Abnormal output ,
underflow	O	underflow Abnormal output
zero	O	Zero output

Next, instantiate the addition module , And then write a tb Functional simulation , The simulation results are shown in the figure below , among inNum1 and inNum2 Two addends ,outNum Is the number of operation results .

Simulation results

5、 ... and 、 summary

        stay FPGA When doing operations, especially floating-point operations , comparison ARM and DSP Always seem unable to do what you want , but FPGA To realize floating-point operation with high speed 、 Low cost 、 Short development cycle and other advantages . And use IP Nuclear development FPGA Can greatly shorten the algorithm in FPGA Cycle implemented on .

        This article is the author's study notes , The author is inexperienced , Limited ability , If there is any mistake, we hope to put it forward .