System Verilog — interface

One 、 Interface

1. Concept

1. take interface Think of it as a “ Insert ”,DUT And TB Data driven relationships between can be used interface This arrangement is used to complete .
2. interface and module The nature of their use is very similar to . It can define ports , Two way signals can also be defined . He can use initial and always, It can also be defined function and task.
3. interface It can be used for design or verification .

2. advantage

1. Encapsulate relevant signals in the same interface , It is beneficial to the maintenance and use of the design and verification environment . If you need to add a new signal , Just declare it once in the interface .
2. Because of the characteristics that can be instantiated , So that for multiple groups of the same bus , Become more flexible when using and instantiating .
3. As SV The only medium of interaction between hardware and software environment in , Both in the hardware world （module） Use in , Or in the software world （class） Use in .

3. Definition and use

Definition ：

1. Definition and module similar , The instantiation method is the same as module equally .
2. stay interface Only the clock needs to be defined in the port list of 、 Reset and other common signals , Or don't define any port signals , Instead, define each need in the variable list DUT and TB Connected logic Variable .
3. interface The reusability can be improved by parameterization .

Use ：

1. Interface signals must be driven using non blocking assignment .
2. When using interfaces, be sure to declare interface variables outside of modules and blocks .
3. Used in an interface modport Group the signals and specify the direction .

// with modport The interface of 
interface arb_if(input bit clk);
	logic[1:0]grant, request;
	logic rst;
	modport TEST(output request, rst,
				 input grant, clk);
	modport DUT(input request, rst, clk,
				output grant);
	modport MONITOR(input request, grant, rst, clk);
endinterface

// Used in the interface modport Arbiter model 
module arb(arb_if.DUT arbif);
	...
endmodule

// Used in the interface modport Test platform of 
module TEST(arb_if.TEST arbif);
	...
endmodule

Two 、 Sampling and driving

1. Competition problem

• In simulation behavior , In order to avoid the timing competition between clock and driving signal in sequential circuit , Drive timing and sampling timing shall be given as clearly as possible .
• By default , The clock will add an infinite minimum time to the driving of the combinational circuit （delta-cycle） Delay of , This delay cannot be measured in absolute time units , Less accurate than the smallest time unit .
• In a time slice （time-slot） Many things can happen in , For example, typing in the simulator “run 0”, That is, let the simulator run a delta-cycle Time for .

How to avoid the competition of sampling ？

• When driving , Add the corresponding artificial delay , Simulate real delay behavior , At the same time, increase clk And the delay between variables , To improve DUT Accuracy and... When using signals TB Reliability when sampling signals .
• For some samples, it still exists delta-cycle Delayed signal , You can also rely on sampling at a certain time before the sampling event , To simulate the sampling requirements of the setup time , Ensure the reliability of sampling .

2.clocking Clock block

• Can be in interface In a statement clocking And the sampled clock signal are used for signal synchronization and sampling .
• clocking The block is based on the clock cycle to drive or sample the signal , bring testbench No longer worry about how to accurately and timely drive or sample the signal , Eliminate the signal competition problem .

// stay clock1 To drive and sample 
clocking [email protected](posedge clock1);
	// stay clock1 Before the rising edge 10ns Input sample it ,
	// After 2ns Drive it out .
	default input #10ns output #2ns
	input ready, margin;
	output data, valid;
endclocking

clocking Use

1. clocking Blocks can not only be defined in interface in , It can also be defined in module and program in .
2. clocking The signals listed in are not self-defined , It should be interface Or any other statement clocking Module defined by .
3. clocking After declaring the name , It should be accompanied by the definition of default sampling events , namely "default input/output event". If there is no definition , Will default to the clocking Before the sampling event 1step Sample the input , After the sampling event #0 Drive the output .
4. In addition to defining default sampling and driving events , You can also define the signal direction , Overwrite the default event with the new sampling event .