DDR SDRAM board design guide

The main topics are as follows ：

• The termination scheme has an impact on the signal quality of the receiving end
• The output driving strength has an impact on the signal quality of the receiving end
• Load type affects signal integrity
  The core goal ： Understand termination types 、 Trade off between output drive strength and load type .

 The key factors affecting the signal quality of the receiving end are as follows ：
 - Leveling and dynamic ODT
 - Proper use of termination
 - Output driver drive strength setting
 - Loading at the receiver
 - Layout guidelines

Leveling and Dynamic ODT

DDR3 and DDR4 SDRAM DIMMs, as specified by JEDEC, always use a fly-by topology for the 
address, command, and clock signals.

Altera recommends that for full DDR3 or DDR4 SDRAM compatibility when using discrete
DDR3 or DDR4 SDRAM components, you should mimic the JEDEC DDR3 or DDR4 fly-by topology
on your custom printed circuit boards (PCB).

Read and Write Leveling

A major difference between DDR2 and DDR3/DDR4 SDRAM is the use of leveling.

In order to improve signal integrity and support higher frequency operation ,JEDEC The Association defines the clock , Command and address bus used fly-by Termination scheme .
read and write leveling stay DDR2 and DDR3 Differences exist , however DDR4 Of Leveling Technology and DDR3 be similar

fly-by The topology deliberately reduces the synchronous switching noise (SSN)