IIC communication

One 、IIC Introduce

I2C Communication protocol (Inter－Integrated Circuit) By Phiilps company-developed , Because it has few pins , The hardware implementation is simple , High scalability , Unwanted USART、CAN And so on , Now it is widely used in many integrated circuits in the system (IC) Communication between .

One I2C The bus uses only two bus lines , A two-way serial data line (SDA) , A serial clock line (SCL). Data lines are used to represent data , The clock line is used for data synchronization .
Each device connected to the bus has a separate address （7bit）, The host can use this address to access different devices .
Bus passing Pull up resistance Connect to the power supply . When I2C When the device is idle , It will output a high resistance state , And when all the devices are idle , When both output high resistance states , Pull the bus to high level by pull-up resistor . I2C The bus is connected to the positive power supply through the pull-up resistor , When the bus is idle , Both wires are high level , The low level of the output of any device connected to the bus , Will lower the signal of the bus , That is to say SDA And SCL All lines “ And ” Relationship .
When multiple hosts use the bus at the same time , To prevent data conflicts , Arbitration will be used to decide which device will occupy the bus .
The start and end signals are sent by the host , After the initial signal is generated , The bus is in the occupied state ; After the termination signal is generated , The bus is idle . Connect to I2C Devices on the bus , If I2C The hardware interface of the bus , It is easy to detect the start and end signals . After the receiver receives a complete data byte , There may be some other work to be done , Such as handling internal interrupt service, etc , The next byte may not be received immediately , At this time, the receiver device can SCL The line is pulled low , So that the host is in a waiting state . Until the receiver is ready to receive the next byte , Re release SCL Line to make it high , So that data transmission can continue .
There are three transmission modes ： The standard mode transmission rate is 100kbit/s , The fast mode is 400kbit/s , It can be reached in high speed mode 3.4Mbit/s, But at present, most of them I2C The device doesn't support high speed mode yet .
Connected to the same bus IC The number is affected by the maximum capacitance of the bus 400pF Limit .

Two 、 IIC The protocol layer of

I2C The protocol defines the start and stop signals for communication 、 Data validity 、 Respond to 、 arbitration 、 Clock synchronization and address broadcast .

Data transfer format

Byte transfer and reply
Each byte must be guaranteed to be 8 Bit length . When data is transmitted , Send the highest bit first （MSB）, Each transmitted byte must be followed by a reply bit （ That is, a frame has 9 position ）. If the response signal from the slave is not received within a period of time , It is automatically considered that the slave has correctly received the data .

Data frame format
A slave address must be sent after the start signal （7 position ）, The first 8 Bit is the transmission direction bit of data （R/T）, use “0” Indicates that the host sends data （T）,“1” Indicates that the host receives data （R）. Every data transmission is always terminated by the termination signal generated by the host . however , If the host wants to continue to occupy the bus for new data transmission , The termination signal may not be generated , Immediately send the start signal again to address another slave .
The host writes data to the slave ：

// Write a byte 
void iic_WByte(u8 data)
{
    
	u8 i;
	for(i=0;i<8;i++)
	{
    
		if(data&0x80)
			SDA_1;
		else
			SDA_0;
	delay();// Prepare the data first 
	SCL_1;
	delay();
	SCL_0;
	delay();
	data<<=1;
	}
}

The host reads data from the slave ：

// Read a byte 
u8 iic_RByte(void)
{
    
	u8 i,rda=0;
	for(i=0;i<8;i++)
	{
    
		rda<<=1;
		SCL_1;
		delay();
		if( read_SDA ==1)
	 rda+=1;
	SCL_0;
	delay();
	}
	return rda;
}

Communication composite format ：

R/W： Transmission direction selection bit ,1 For reading ,0 For writing
Start and stop signals of communication

When SCL The line is at high level SDA The line switches from high level to low level , Indicates the start of communication .
When SCL The line is at high level SDA The line switches from low level to high level , Indicates that communication has stopped .
Start and stop signals are usually generated by the host computer .

void iic_start(void)
{
    
	SDA_1;
	SCL_1;
	delay();
	SDA_0;
	delay();
	SCL_0;  // Hold on I2C Bus , Ready to send or receive data 
}
void iic_stop(void)
{
    
	SDA_0;
	delay();
	SCL_1;
	delay();
	SDA_1;
	delay();

}

Data validity
I2C Use SDA Signal lines to transmit data , Use SCL Signal line for data synchronization ,SDA The data line is in SCL One bit of data per clock cycle .

SCL When it's high level SDA The data represented is valid , That at this time SDA Show data for high level “1”, Show data for low level “0”. When SCL Low power level ,SDA Invalid data for , Usually at this time SDA Carry out level switching （ send data ） Prepare for the next presentation of data .
Address and data direction
I2C Each device on the bus has its own independent address , When the host initiates communication , adopt SDA Signal line sending device address (SLAVE_ADDRESS) To find the slave . The device address can be 7 Bit or 10 position .
A data bit immediately following the device address R/W Used to indicate the direction of data transmission , The data direction bit is “1” Indicates that the host reads data from the slave , This bit is “0” Indicates that the master writes data to the slave .

Respond to
I2C The data and address of the transmission are with response . Responses include “ The reply (ACK)” and “ Non response (NACK)” Two signals .

The host generates a clock during transmission , In the 9 When it's a clock , The data sender will release SDA Control right , Controlled by the data receiver SDA, if SDA High level , Indicates a non response signal (NACK), A low level indicates a reply signal (ACK)

void iic_ask(void)
{
    
	SDA_0;
	SCL_1;
	delay();
	SCL_0;
	delay();
	SDA_1;  // Release control 
	delay();
	
}
void iic_Nack(void)
{
    
	SDA_1;
	SCL_1;
	delay();
	SCL_0;
	delay();
}
// Waiting for an answer  ask：0 nask：1
u8 iic_wa()
{
    
	u8 reply;
	SDA_1;  // Release control 
	SCL_1;
	delay();
	if( read_SDA ==1)
	 reply=1;
	else
		reply=0;
	SCL_0;
	delay();
		return reply;
}