Introduction to interface in SystemVerilog

interface Background

With the increase of design complexity , The connection between modules has also become more complex . Two RTL There may be dozens of connection signals between modules , These signals must be arranged in the correct order for them to communicate correctly . When adding a new signal to two modules , Not only do you need to edit the module code to add new ports , You also need to edit the net list code of the connecting device in the upper level , Errors at any level will cause the design to fail to work properly .

traditional method ： Signal connection method using signal name mapping , But this undoubtedly increases the amount of code input , And it's easy to make mistakes .

terms of settlement ： Use interface , It is systemVerilog One of them represents a bundle of wires , It is a code with intelligent synchronization and connection functions . An interface can be instantiated like a module , It can also be connected to the port like a signal line .

Interface function ：

Interfaces contain connections 、 Sync 、 Even the communication function between two or more blocks , They connect the design block and the test platform . 

Illustrate with examples ：

（1） Arbiter interface ：

interface arb_if(input bit clk);
logic [1:0] grant,request;
logic rst;
endinterface

 （2） Arbitrators using interfaces

module arb (arb_if arbif);
...
  always @(posedge arbif.clk or posedge arbif.rst) begin
    if(arbif.rst)
       arbif.grant<=2'b00;// Transmit data to the interface 
    else
       arbif.grant<=next_grant;
...
end
endmodule

（3） Test platform using arbiter interface

module test (arb_if arbif)
...
  initial begin
  // The reset code is omitted here 
   @(posedge arbif.clk) arbif.request <=2'b01;
   $display("@%0t: Drove req=01",$time);
   repeat (2) @(posedge arbif.clk);
   if(arbif.grant !=2'b01) $display("@%0t:al:grant!=2'b01",$time);
$finish
end
endmodule : test

（4） Using the arbiter interface top modular

module top;
bit clk;
always #5 clk=~clk;
arb_if arbif(clk);
arb_al (arbif);
test_t1(arbif);
endmodule : top

Example benefits ：

Connections become simpler and less error prone . If you want to put a new signal into an interface , You only need to make changes in the interface definition and the modules that actually use this interface . You don't need to change any other modules , For example, in top modular , The signal just passes through the module , Without any operation . This feature greatly reduces the probability of connection errors .

=================== Do not conform to the Verilog-2001 Old code processing method ================

If you can't meet Verilog-2001 Modify the old source code , Change the port into an interface , You can connect the signal of the interface directly to each port . In the following example arb_port Code module .