systemVerilog中automatic用法

//有 "automatic"

module tryfact;

// define the function
function automatic integer factorial (input [31:0] operand);
if (operand >= 2)
    factorial = factorial (operand - 1) * operand;
else
    factorial = 1;
endfunction: factorial

// test the function
integer result;
initial begin
    for (int n = 0; n <= 7; n++) begin
        result = factorial(n);
        $display("%0d factorial=%0d", n, result);
    end
end
endmodule: tryfact

The simulation results are as follows:
0 factorial=1
1 factorial=1
2 factorial=2
3 factorial=6
4 factorial=24
5 factorial=120
6 factorial=720
7 factorial=5040

//没有automic

The simulation results are as follows:
0 factorial=1
1 factorial=1
2 factorial=1
3 factorial=1
4 factorial=1
5 factorial=1
6 factorial=1
7 factorial=1

简单的说：如果声明为automic的函数,任务,则支持迭代,否则不支持.