Axi low power interface

Interface signal

CSYSREQ

The system clock controller pulls down CSYSREQ To request the device to enter a low power state ;
The system clock controller is pulled up CSYSREQ To request the device to exit the low power state .

CSYSACK

The equipment is pulled down CSYSACK To respond to the request of the system clock controller to enter the low power state ;
Equipment is raised by pulling CSYSACK To respond to the request of the system clock controller to exit the low power state .

CACTIVATE

CACTIVATE Used to indicate whether the device needs a clock signal .

sequential

The device accepts a low power request

stay T1 moment , The system clock controller drives CSYSREQ by LOW, To request peripheral devices to enter a low power state . After the peripheral recognizes the request , It performs its power down sequence , stay T2 It drives all the time CACTIVATE For low . And then in T3 moment , Peripheral drive CSYSACK by LOW, It indicates that it has entered a low-power state .

Device rejects low power request

stay T1 moment , The system clock controller drives CSYSREQ by LOW, To request peripheral devices to enter a low power state . stay T2 when , Peripherals remain CACTIVATE For the high , And pull down CSYSACK To respond , Indicates that the request is rejected . stay T3 moment , The system clock controller drives CSYSREQ Exit low power state for high . stay T4 moment , The periphery is driven by CSYSACK Respond to high , To exit the low power state .

Exit the low power state

System clock controller or Peripherals Can request to exit from the low power state .

System clock controller initiated exit

stay T1 moment , The system clock controller drives CSYSREQ For the high , Request to exit the low power state , Then enable the clock . The peripheral recognizes CSYSREQ It's high , Perform its power on sequence , And in T2 drive CACTIVATE For the high , To show that it needs a clock signal . then , Peripheral devices are driven by CSYSACK For the high , stay T3 Low power exit request completed at .

Peripheral initiated exit

stay T1 moment , Peripheral drive CACTIVATE For the high , Indicates that it requires a clock signal . then , The system clock controller must restore the clock . stay T2 when , The system clock controller drives CSYSREQ For the high . The peripheral device completes its exit from the low power state , And drive CSYSACK High to complete the exit of low power state .

flow chart

Flow chart for entering low power state

Flow chart for exiting the low power state