[Verilog] sub module connection related problems (adder and Its Optimization)

One . adopt wire Variables achieve the interconnection of different sub modules

We create wire Variable interworking of these sub modules q→d, Then connect the sub module with the top-level module through the port name ：

The procedure is as follows ：

Write the knowledge you need to know about this program ：
① Definition of sub module , Declaration and call （ Instantiation ）.
② Connection method between sub module and top layer （by name）.
③wire Variables store binary signals , Thus, it plays a role of undertaking .
【 Practice address links ：Module shift】

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Two . A slightly more complex example

Be careful ：
① This example requires not only interconnected sub modules , And it needs to transmit multi bit signals .
② The key step is in the last four 8 Bit signal passes “ Signal selector ”（ Trapezoidal element ）, And by a two bit signal sel Control output . The realization of signal selector needs the help of [email protected](*) sentence .

The picture below is wire And some names of examples ：

The procedure is as follows ：

【 Practice address links ：Module shift8】

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3、 ... and . Design of adder

As shown in the picture 32 The bit adder is a 32 The signal of bit is split into “ high 16 position ” and “ low 16 position ”, Separate operation and integration . among cin and cout Control and control “ carry ”： low 16 The carry of bit operation passes cout Transferred to the cin, low 16 Bit initialization has no carry value , So low 16 Bit adder passed cin==0. therefore , Every adder actually operates a+b+cin.

The above adder is actually “ Full adder ”, Its interior is composed of several “ Half adder ” Made up of ：

Each half adder （ In the picture add1） Only two can be operated 1 Addition of bit signals . It's not hard to see. , One “16 Bit full adder ” By 8 individual “ Half adder ” Made up of .

The half adder inputs two one bit signals , Output two signals ：“ and ” and “ carry ”, Logic gates are as follows ：

sum = a ^ b ^ cin
cout = a&b | a&cin | b&cin

Now? , We do this through code “ Half adder ”：
（ We need to consider the logic gate design of half adder , There is no need to consider the connection between half adders ）

【 Practice address links ：Module fadd】

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Four . Adder optimization

“ low 16 position ” The adder passes cout towards “ high 16 position ” Transmit carry signal , The delay in this process is quite large , Need to optimize ：

The optimization method is ： Make one more copy ” high 16 position “ adder , But a cin=1, the other one cin=0. adopt “ low 16 position ” The output carry signal controls a “ Selectors ”, Choose one “ high 16 position ” The result of the operation , Finally, integrate . This avoids “ high 16 position ” and “ low 16 position ” Signal transmission between adders , Reduced latency .

The specified names are as follows ：

The top-level program is as follows ：

【 Practice address links ：Module cseladd】