【数字IC/FPGA】检测最后一个匹配序列的位置

题目描述

编写一个模块，输入一个64比特的比特流，识别匹配出101101的最后的位置，并输出位置信息。

代码

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/06/21 10:34:41
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module top(
input logic clk,
input logic rst,
input logic valid,
input logic din,
output logic done,
output logic [5:0] pos
);
//101101
logic [5:0] shift_reg;
logic [5:0] cnt;
//cnt
[email protected](posedge clk,posedge rst)
if(rst)
   cnt<=0;
else if(valid)
begin
   if(cnt==64-1)
      cnt<=0;
   else
      cnt<=cnt+1;
end
//shift_reg
[email protected](posedge clk,posedge rst)
if(rst)
   shift_reg<=0;
else if(valid)
   shift_reg<={
    shift_reg[4:0],din};                       //高位先输入
//pos
[email protected](posedge clk,posedge rst)
if(rst)
begin
    pos<=64;           
end
else if(shift_reg==6'b101101)
begin
   pos<=cnt-6;
end
//done
[email protected](posedge clk,posedge rst)
if(rst)
   done<=0;
else
   done<=(cnt==64-1&&valid)?1:0;
endmodule

测试平台

module test;
logic clk;
logic rst;
logic valid;
logic din;
logic done;
logic [5:0] cnt;
logic [5:0] pos;
logic [63:0] data;
//
initial
begin
   //data={12'b101101101101,52'd0};
   data={
    20'd0,12'b101101101101,32'd0};
end
//clk
initial
begin
   clk=0;
   forever
      #5 clk=~clk;
end
//rst
initial
begin
   rst=1;
   #100
   rst=0;
end
//valid,din
initial
begin
   valid<=0;
   cnt<=0;
   wait(rst==1'b0);
   @(posedge clk);
   repeat(64)
   begin
      valid<=1;
	  din<=data[63-cnt];
	  cnt<=cnt+1;
	  @(posedge clk);
   end
   valid<=0;
end



top U(.*);
/* input logic clk, input logic rst, input logic valid, input logic din, output logic done, output logic [5:0] pos ); */
endmodule

结果

输入比特流为data={20’d0,12’b101101101101,32’d0}，因此，最后匹配的序列的位置应该是20+6=26，符合预期。