SystemVerilog (12) - $unit declaration space

note
$unit Is a dangerous shared namespace , Full of danger . Its use will make the design difficult to compile and maintain .
The following unit representative $unit

Will be package Add to SystemVerilog Before standard ,SV Provides a different mechanism to create definitions shared by multiple modules . This mechanism is called unit Pseudo global namespace of , Also known as unit Compile unit or declaration space . Any declaration outside the declaration space is in unit In the declaration space . In the following example ,bool_t Is defined outside of two modules , So in unit In the declaration space .

unit A declaration space can contain the same as package User defined of the same type , And have the same comprehensive limitations . However , Unlike the bag ,unit Declaration space can make design code difficult to maintain ,EDA It is also difficult to compile . Use unit Some of the dangers of include

• With unit The definition of a declaration space can be scattered across many files , Make code maintenance and code reuse a nightmare , When referencing user-defined types in the package 、 Mission 、 Function or other identifier name , The definition of identifier names is relatively easy to find and maintain . There is always an explicit package reference or package import statement to show where the definition can be found . When in unit User defined types are defined in the declaration space 、 Mission 、 Function or other identifier , This definition can be found in any file that makes up the source code for the design and verification test bench 、 Any directory 、 In any server . location 、 It is difficult to maintain and redefine .

• When unit When a definition in a declaration space is in more than one file , These files must be compiled in a specific order .

SystemVerilog Requires that the definition be compiled before it is referenced . When unit When declarations are scattered in many files , Compiling all the files in the right order can be difficult , It's not even possible .

• change unit Define all source code files that need to be recompiled .

Yes unit Any changes defined in the declaration space require recompiling all the source code that makes up the design and validation testbed , Because any file anywhere can use this definition without importing . Many software tools do not force recompilation of all files , But if you don't recompile , Design modules may end up using outdated definitions .

• For simulation and synthesis ,unit The declaration space can be the same , But it's usually different .

Each call to the compiler starts a new unit Declaration space , This space does not share other unit Declarations in the declaration space . many SystemVerilog The emulator compiles multiple files together . These tools will see a unit Space . In a file unit The definition is visible to any subsequent files in a single compilation . majority SystemVerilog Integrated compilers and some emulators support separate file compilation , Each file can be compiled independently . These tools will see several disconnected unit Declaration space . In a file unit The definition is not visible to any other file .

• It's easy to have duplicate identifier names with different definitions .

stay SystemVerilog in , It is illegal to define the same name more than once in the same namespace . If a document is in unit The declaration space defines bool_t User defined types , And the other file is in unit The declaration space also defines bool_t User defined types , Then these two files can never be compiled together , Because these two definitions will eventually be in the same unit End in space . To avoid this conflict , The engineer must use ’define and ’ifdef Add conditional compilation instructions , So that only the first definition encountered by the compiler is compiled .

Packages can be imported into unit in , But its harm is directly related to unit Hazards defined in . Besides , Care must be taken not to import the same package into the same... Multiple times unit Declaration space , It's illegal .

Best practice guide 4-2
Avoid like Bubonic plague The use of $unit！ contrary , Use packages to share definitions .
Package avoided $unit All hazards , Packages provide a controlled declaration space that is easy to maintain and reuse .

SystemVerilog( Ten )- User defined types

SystemVerilog( 11、 ... and )-SystemVerilog package