Page table cache of Linux kernel source code analysis

         Memory unit of processor （MMU） Responsible for converting virtual addresses into physical addresses . In order to improve the conversion speed from virtual address to physical address , introduce TLB The cache of . Namely page table cache

         The page table cache is used to cache recently used page table entries , Some processors use a two-level page table cache ： first stage TLB Divided into instructions TLB And data TLB, Level second TLB It's unity TLB, That is, instructions and data are common TLB

TLB management

If the kernel modifies the cache in TLB Data in , Then the old data must be abolished , How does the kernel ensure consistency ？

function
flush_tlb_all	Make all TLB invalid
flush_tlb_mm	Make all of the specified user address space TLB invalid
flush_tlb_range	Make the specified address space range TLB invalid
flush_tlb_page	Make the specified virtual address page in the specified user address space TLB The entry is invalid
flush_tlb_kernel_range	Make the kernel virtual address range TLB The entry is invalid
update_mmu_cache	After modifying the page table entry, set the page table entry to the page table cache , The processor that manages the page table cache by software must implement this function .
tlb_migrate_finish	After the kernel migrates processes from one processor to another , Call this function to update the page table cache or context specific information .

When TLB When you miss ,ARM64 The memory management unit of the processor automatically traverses the page table in memory , Copy page entries to TLB, There is no need for software to write the page table TLB, therefore ARM64 The schema does not provide write TLB Instructions .

#define isb()		asm volatile("isb" : : : "memory")
#define dmb(opt)	asm volatile("dmb " #opt : : : "memory")
#define dsb(opt)	asm volatile("dsb " #opt : : : "memory")

#define __TLBI_1(op, arg) asm ("tlbi " #op ", %0\n"			       \
		   ALTERNATIVE("nop\n			nop",		       \
			       "dsb ish\n		tlbi " #op ", %0",     \
			       ARM64_WORKAROUND_REPEAT_TLBI,		       \
			       CONFIG_ARM64_WORKAROUND_REPEAT_TLBI)	       \
			    : : "r" (arg))

#define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg)

#define __tlbi(op, ...)		__TLBI_N(op, ##__VA_ARGS__, 1, 0)

static inline void flush_tlb_all(void)
{
	dsb(ishst);
	__tlbi(vmalle1is);
	dsb(ish);
	isb();
}

  The expanded procedure is

static inline void flush_tlb_all(void)
{
    // Ensure that the stored instructions in front of the barrier are executed ,dsb It's data synchronization ,ish Indicates that the shared domain is an internal share ,st Indicates storage 
	asm volatile("dsb  ishst" : : : "memory");
    // Make all cores match the current VMID, Stage 1 And exception level 1 All of the TLB The entry is invalid 
	asm ("tlbi vmallelis" : :);
    // Make sure TLB The previous instructions have been executed 
    asm volatile("dsb  ish" : : : "memory");
    // Command synchronization barrier , Instructions wash the pipeline of the processor , Reread all instructions following the barrier instruction 
	asm volatile("isb" : : : "memory")
}

 local_flush_tlb_all Used to make all of the current core TLB The entry is invalid

static inline void local_flush_tlb_all(void)
{
	dsb(nshst);
	__tlbi(vmalle1);
	dsb(nsh);
	isb();
}

And the function flush_tlb_all The difference is as follows

1） Instructions dsb Medium ish Instead of nsh,nsh Yes no share , Indicates that the data synchronization barrier instruction only works in the current core

2） Instructions tlbi Not carrying is, Means to make only the current core TLB The entry is invalid .

Address space identifier

         To reduce the need to empty the page table cache during process switching ,ARM64 The processor's page table cache uses non global bits to distinguish between kernel and process page table entries . Use an address space identifier ASID（Address Space Identifier） Distinguish the page table entries of different processes .

Virtual machine identifier

         The virtual address of the guest operating system running in the virtual machine is changed into the physical address in two stages ： The first 1 Stage virtual Address conversion to intermediate physical address , The first 2 Phase converts intermediate physical addresses into physical addresses . The first 1 The phase transition is operated by the customer Memory control of the system , The conversion process is the same as that of non virtualization . The first 2 Phase transitions are controlled by the virtual machine monitor , Virtual machine monitor The controller maintains a conversion table for each virtual machine , Assign a virtual machine identifier （Virtual Machine Identifier,VMID）, register VTTBR_EL2（ Virtualization conversion table reference register ,Virtualization Translation Table Base Register） The stage where the current virtual machine is stored 2 Translate the physical address of the table .

Reference link

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