Summary of config mechanism and methods in UVM (1)

During the creation of the verification environment build phase in , In addition to the component instantiation process , The configuration phase is also essential . To verify the reusability of the environment , Configure through external parameters , This enables the environment to select the components to be created according to different parameters 、 Number of instances of component 、 The connection between components and the operation mode of components, etc . Adjust in a more detailed environment （environment tuning） in , There are more variables to configure , for example for-loop The threshold of 、 String name 、 The generating proportion of random variables, etc . No matter what parameters are configured , Users can set at compile time or simulation time . To adjust these variables in compile time , You can change the parameters 、 Or introduce preprocessing instructions （compiler directive, for example ifdef/ifndef/else/elsif/`endif） To modify the . Compared to recompiling , In the simulation, you can modify the environment by setting variables , It is more flexible , and UVM config The mechanism is the way to do this .
UVM Provides uvm_config_db And several convenient variable setting methods to realize the environment control during simulation . common uvm_config_db The ways of using include ：
1. Pass on virtual interface Into the environment .
2. Set a single variable value , for example int、string、enum etc. .
3. Pass configuration object （config object） To the environment .
The following paragraphs are examples to illustrate these methods .
1.interface Pass on
So let's see first interface The transfer , Through this convenient way of transmission, the connection between the hardware world and the software world is well solved . And before about SV In the core chapter of , Readers can see , although SV You can do this by layering interface To complete the delivery , But this method is not conducive to the encapsulation and reuse of software environment . This way , Make the interface transfer and acquisition completely separate , And in the background virtual interface The one who made a contribution to the transmission of uvm_config_db.

interface intf1;
  logic enable = 0;
endinterface

module config_interface;
  import uvm_pkg::*;
  `include "uvm_macros.svh"

  class comp1 extends uvm_component; 
    `uvm_component_utils(comp1)
    virtual intf1 vif;
    function new(string name, uvm_component parent);
      super.new(name, parent);
    endfunction
    function void build_phase(uvm_phase phase);
      if(!uvm_config_db#(virtual intf1)::get(this, "", "vif", vif)) begin
        `uvm_error("GETVIF", "no virtual interface is assigned")
      end
      `uvm_info("SETVAL", $sformatf("vif.enable is %b before set", vif.enable), UVM_LOW)
      vif.enable = 1;
      `uvm_info("SETVAL", $sformatf("vif.enable is %b after set", vif.enable), UVM_LOW)
    endfunction
  endclass

  class test1 extends uvm_test;
    `uvm_component_utils(test1)
    comp1 c1;
    function new(string name, uvm_component parent);
      super.new(name, parent);
    endfunction
    function void build_phase(uvm_phase phase);
      c1 = comp1::type_id::create("c1", this);
    endfunction
  endclass

  intf1 intf();

  initial begin
    uvm_config_db#(virtual intf1)::set(uvm_root::get(), "uvm_test_top.c1", "vif", intf);
    run_test("test1");
  end
endmodule

Output results

UVM_INFO @ 0: reporter [RNTST] Running test test1...
UVM_INFO @ 0: uvm_test_top.c1 [SETVAL] vif.enable is 0 before set
UVM_INFO @ 0: uvm_test_top.c1 [SETVAL] vif.enable is 1 after set

As you can see from the above example , The interface passes from the hardware world to UVM The delivery in the environment can be through uvm_config_db To achieve . There are several points to pay attention to in the implementation process ：
The interface transfer should take place in run_test() Before . This ensures that before entering build phase Before ,virtual interface Has passed into uvm_config_db in .
Users should put interface And virtual interface The declaration of . The type in the transfer process should be virtual interface, That is, the handle of the actual interface .

2. Variable is set
In all test in , Can be in build phase Phase configures variables in the underlying components , Then complete the configuration before the environment instantiation , Make the environment work as expected .

module config_variable;
  import uvm_pkg::*;
  `include "uvm_macros.svh"

  class comp1 extends uvm_component; 
    `uvm_component_utils(comp1)
    int val1 = 1;
    string str1 = "null";
    function new(string name, uvm_component parent);
      super.new(name, parent);
    endfunction
    function void build_phase(uvm_phase phase);
      `uvm_info("SETVAL", $sformatf("val1 is %d before get", val1), UVM_LOW)
      `uvm_info("SETVAL", $sformatf("str1 is %s before get", str1), UVM_LOW)
      uvm_config_db#(int)::get(this, "", "val1", val1);
      uvm_config_db#(string)::get(this, "", "str1", str1);
      `uvm_info("SETVAL", $sformatf("val1 is %d after get", val1), UVM_LOW)
      `uvm_info("SETVAL", $sformatf("str1 is %s after get", str1), UVM_LOW)
    endfunction
  endclass

  class test1 extends uvm_test;
    `uvm_component_utils(test1)
    comp1 c1;
    function new(string name, uvm_component parent);
      super.new(name, parent);
    endfunction
    function void build_phase(uvm_phase phase);
      uvm_config_db#(int)::set(this, "c1", "val1", 100);
      uvm_config_db#(string)::set(this, "c1", "str1", "comp1");
      c1 = comp1::type_id::create("c1", this);
    endfunction
  endclass

  initial begin
    run_test("test1");
  end
endmodule

Output results

UVM_INFO @ 0: reporter [RNTST] Running test test1...
UVM_INFO @ 0: uvm_test_top.c1 [SETVAL] val1 is 1 before get
UVM_INFO @ 0: uvm_test_top.c1 [SETVAL] str1 is null before get
UVM_INFO @ 0: uvm_test_top.c1 [SETVAL] val1 is 100 after get
UVM_INFO @ 0: uvm_test_top.c1 [SETVAL] str1 is comp1 after get

3. config object Pass on
   In practice test Configuration in progress , The number of parameters to be configured is not only large , It also belongs to different components . that , If you make a single variable setting similar to the above for variables in so many levels , On the one hand, more code is needed , This is error prone , Not easy to read , On the other hand, it is not easy to reuse , After all, the variables of the underlying components have been added or reduced , adopt uvm_config_db::set It is impossible to know whether the setting is successful . therefore , If you integrate the variables in each component , First place in a uvm_object Is used to pass , It will be more conducive to the overall configuration .

  import uvm_pkg::*;
  `include "uvm_macros.svh"

  class config1 extends uvm_object;
    int val1 = 1;
    int str1 = "null";
    `uvm_object_utils(config1)
    function new(string name = "config1");
      super.new(name);
    endfunction
  endclass

  class comp1 extends uvm_component; 
    `uvm_component_utils(comp1)
    config1 cfg;
    function new(string name, uvm_component parent);
      super.new(name, parent);
    endfunction
    function void build_phase(uvm_phase phase);
      uvm_object tmp;
      uvm_config_db#(uvm_object)::get(this, "", "cfg", tmp);
      void'($cast(cfg, tmp));
      `uvm_info("SETVAL", $sformatf("cfg.val1 is %d after get", cfg.val1), UVM_LOW)
      `uvm_info("SETVAL", $sformatf("cfg.str1 is %s after get", cfg.str1), UVM_LOW)
    endfunction
  endclass

  class test1 extends uvm_test;
    `uvm_component_utils(test1)
    comp1 c1, c2;
    config1 cfg1, cfg2;
    function new(string name, uvm_component parent);
      super.new(name, parent);
    endfunction
    function void build_phase(uvm_phase phase);
      cfg1 = config1::type_id::create("cfg1");
      cfg2 = config1::type_id::create("cfg2");
      cfg1.val1 = 30;
      cfg1.str1= "c1";
      cfg2.val1 = 50;
      cfg2.str1= "c2";
      uvm_config_db#(uvm_object)::set(this, "c1", "cfg", cfg1);
      uvm_config_db#(uvm_object)::set(this, "c2", "cfg", cfg2);
      c1 = comp1::type_id::create("c1", this);
      c2 = comp1::type_id::create("c2", this);
    endfunction
  endclass

  initial begin
    run_test("test1");
  end
endmodule

Output results

UVM_INFO @ 0: reporter [RNTST] Running test test1...
UVM_INFO @ 0: uvm_test_top.c1 [SETVAL] cfg.val1 is 30 after get
UVM_INFO @ 0: uvm_test_top.c1 [SETVAL] cfg.str1 is c1 after get
UVM_INFO @ 0: uvm_test_top.c2 [SETVAL] cfg.val1 is 50 after get
UVM_INFO @ 0: uvm_test_top.c2 [SETVAL] cfg.str1 is c2 after get