Introduction to armv8 general timer

Preface

Sort out and summarize relevant concepts based on online materials , Part of the content is quoted from the following article .

1 Generic timer One

The content is quoted from the article “Linux One of the time subsystems （ seventeen ）：ARM generic timer Driver code analysis ”, Put the link at the end of the text .

1.1 system counter

ARM generic timer Related hardware block As shown in the figure below （ Mark it in green ）：

ARM generic timer The hardware block Mainly SOC Upper System counter（ Multiple process share , Used to record the passage of time ） And attached to each processor Upper Timer（ Used to trigger timer event） form , Other generic timer The hardware circuit of is mainly used for communication generic time event Of . For example, each processor Medium timer and system counter Peripherals interact , each processor Medium timer Information exchange .System counter Its function is very simple , It is to calculate how many input clocks have passed clock, The beginning was 0, every last clock,System counter Will add one .System counter Of counter value It needs to be distributed to all timer in , in other words , From each timer From the perspective of ,system counter value It should be consistent .Timer It's actually a timer , It can define a specified time , When it's time , will assert An external output signal （ It can be output to GIC, As a interrupt source）.

from power domain Look at ,ARM generic timer Divided into two parts ：System counter And each Multiprocessor In the system Timer_x、 Interface circuit, etc . The reason for this is obvious ： Power consumption （ Power management ） Consideration . stay power saving mode Next , Sure shutdown each processor Power supply of the system , But you can keep system counter Power supply of , such , At least the system time can be maintained .

and power domain similar ,clock domain It's also different ,system counter and processor Work in different clock Next , The software has been modified CPU The frequency of will not affect system counter Work rhythm of , It will not change timer act .

1.2 Physical counter

each cpu Of timer It's based on system counter To trigger timer event Of , therefore , There must be a mechanism in the system to make System counter The value of is broadcast to each CPU Of timer HW block On , Run in all at the same time processor The software on can be obtained through the interface System counter Value .

The processor can use CNTPCT Register to get system counter The current value of the , We call it physical counter.

Yes physical There is virtual,processor Can pass CNTVCT Register access virtual counter, however , For not supporting security extension and virtualization extension The system of ,virtual counter and physical counter It's the same value .

1.3 Timers

Every... In the system processor Will attach multiple timer, As follows ：

（1） For not supporting security extension Of SOC（ I won't support it security extension That means I won't support it virtualization extension）,timer There are actually two , One is physical timer, The other is virtual timer. Although there are two , But in terms of behavior ,virtual timer and physical timer Act in concert

（2） For support security extension But does not support virtualization extension Of SOC, Every cpu There are three timer：Non-secure physical timer,Secure physical timer and virtual timer

（3） For support virtualization extension Of SOC, Every cpu There are four timer：Non-secure PL1 physical timer,Secure PL1 physical timer,Non-secure PL2 physical timer and virtual timer

Every timer There will be three registers （ We use it physical timer As an example ）：

（1）64-bit CompareValue register. This register matches system counter You can implement a 64 bit unsigned upcounter. If physical counter - CompareValue >= 0 Words , Trigger interrupt . in other words ,CompareValue register It's really just a 64 Bit upcounter, Set to a higher value than the current system counter Larger value , With system counter The continuous accumulation , When system counter value touch CompareValue register When setting the value , You're going to GIC Trigger interrupt .

（2）32-bit TimerValue register. This register matches system counter You can implement a 32 bit signed downcounter（ sometimes , Use downcounter It will make software logic easier , see ARM generic timer How thoughtful the designers are ）. At the beginning , We can set TimerValue The value of the register is 1000（ Suppose we want to down count 1000, Then trigger the interrupt ）, Write to this register 1000 In fact, it is set CompareValue register The value of is system counter Value plus 1000. With system counter The value of is accumulating ,TimerValue register The value of is decreasing , On duty <=0 When , You're going to GIC Trigger interrupt

（3）32-bit Control register . This register is mainly for timer Control , Specific include ：enable or disable The timer,mask perhaps unmask The timer Of output signal（timer interrupt）

each processor Each of them Timer Can generate interrupts , So it and GIC Interface with . Of course , because timer The interrupt of belongs to each CPU Of , Therefore use PPI Type of interrupt , For details, please refer to GIC file . Of course , If you allow timer Trigger interrupt , Of course, make sure that timer yes enable And is umask Of .

2 Generic timer

Quote article “ARMV8 datasheet Learning notes 4：AArch64 System level architecture Generic timer”, Put the link at the end of the text .

2.1 summary

 2.2  complete generic timer Components

 2.3 System Counter

2.4  AArch64 generic timer

2.4.1 Physical counter（ contain system connter Of count value ）

 2.4.2  Multiple timers

Reference resources

1、 author	post
	Arm Introduction to general timer
	【ARMv8】 General timer summary
	ARMV8 datasheet Learning notes 4：AArch64 System level architecture Generic timer
	Linux One of the time subsystems （ seventeen ）：ARM generic timer Driver code analysis
	Linux Drive development Thirty-four ：Linux Principle of kernel timer