FPGA - 7 Series FPGA selectio -06- odelay of logic resources

Preface

Excerpts from this article UG471 Chapter two of , Organize and translate , Used to introduce SelectIO Resource internal ODELAY resources .

ODELAY Resource profile

Output delay resource (ODELAY) stay HR Bank Unavailable in . Every HP I/O Each module contains a named ODELAYE2 Programmable absolute delay primitive for .ODELAY Can be connected to OLOGICE2/OSERDESE2 block . ODELAY It's a 31 Takeout 、 Wrap delay primitive , With calibrated tap resolution . Delay value see 7 series FPGA Data manual . It can be applied to composite output paths or registered output paths . It can also directly from FPGA Logical access . ODELAY It is allowed to delay the output signal separately . By getting from 7 series FPGA Select one of the ranges specified in the data manual IDELAYCTRL Change the tap delay resolution by referring to the clock .

ODELAYE2 The original language

The image below shows ODELAYE2 The original language .

ODELAYE2 port

The port overview table is as follows ：

Port Name	Direction	Width	Function
C	Input	1	stay VARIABLE、VAR_LOAD or VAR_LOAD_PIPE Clock input used in mode .
REGRST	Input	1	Reset the pipeline register to all zeros .
LD	Input	1	take ODELAY The primitive is loaded into VARIABLE Pre programmed value in mode . stay VAR_LOAD In mode , It is loaded CNTVALUEIN Value . stay VAR_LOAD_PIPE In mode , It loads the value currently in the pipeline register .
CE	Input	1	Enable incremental / Decreasing function .
INC	Input	1	increase / Reduce the number of tap delays .
CINVCTRL	Input	1	Dynamic reverse clock Polarity .
CNTVALUEIN	Input	5	come from FPGA Input value of logic , Used to dynamically load tap values .
CLKIN	Input	1	Clock access ODELAY（ come from I/O CLKMUX）.
ODATAIN	Input	1	come from OLOGICE2/OSERDESE2 Of ODELAY data input .
LDPIPEEN	Input	1	Enables pipelined registers to be transferred from CNTVALUEIN Load data .
DATAOUT	Output	1	From two data input ports （ODATAIN and CLKIN） One of the delay data .
CNTVALUEOUT	Output	5	The current delay value enters FPGA Logic to monitor tap values .

Port Introduction

come from FPGA OLOGICE2/OSERDESE2 Data input of - ODATAIN

ODATAIN Input by OLOGICE2/OSERDESE2 drive . ODATAIN The driver is connected to IOB Of DATAOUT port , Delay by ODELAY_VALUE Set up .

Clock input from clock buffer - CLKIN

CLKIN Input by clock buffer （BUFIO、BUFG or BUFR） drive . then , At this time, the clock will be delayed by a setting of ODELAY_VALUE Value , And pass DATAOUT And the output buffer （OBUFT or OBUFTDS） Output . When using IOBUF when , Delayed clocks can be routed back FPGA Logic . When using IOBUF Route the clock back FPGA when , Will use FPGA Package pins of .

Data output - DATAOUT

Delay data from one of the two data input ports . DATAOUT Connect to IOB.

Clock input - C

ODELAYE2 The original language （LD、CE and INC） All control inputs and clock inputs of Sync . When ODELAY Configure to VARIABLE、VAR_LOAD or VAR_LOAD_PIPE Mode time , The clock must be connected to this port . C It can be partially reversed , And must be provided by the global or regional clock buffer . The clock must be connected to the SelectIO The same clock used in the logical resource . for example , When using OSERDESE2 when ,C Connect to and CLKDIV The same clock . If IDELAYE2 Primitive and ODELAYE2 The primitive is in the same I/O bank Use in ,C You must use the same clock network for both primitives .

Module loading - LD

stay VARIABLE In mode ,ODELAY Load port LD Load the delay primitive into the ODELAY_VALUE property . If these attributes are not specified , The value is assumed to be zero . LD The signal is a high level active signal , And input clock signal Sync .

stay VAR_LOAD In mode ,ODELAY Load port LD Load the delay primitive into the CNTVALUEIN Set the value of the . CNTVALUEIN[4:0] The value at will be the new tap value . Because of this function ,ODELAY_VALUE Attribute ignored .

stay VAR_LOAD_PIPE In mode ,IDELAY Load port LD Load the current value in the pipeline register . The value in the pipeline register will be the new tap value .

Pipeline register loading - LDPIPEEN

High voltage usually , This input will be currently in CNTVALUEIN The value on the pin is loaded into the pipeline register .

Pipeline register reset - REGRST

When it is high , This input resets the pipeline register to all zeros .

C Pin polarity switching - CINVCTRL

CINVCTRL Pins are used for dynamic switching C Polarity of pin . This applies to applications where failure is not a problem . When switching polarity , Do not use in two clock cycles ODELAY Control pin .

Count value input - CNTVALUEIN

CNTVALUEIN Pin and LD Pins are used together to dynamically switch loadable tap values .

Count value output - CNTVALUEOUT

CNTVALUEOUT The pin is used to report the loaded tap value .

The incremental / Decrement signal - CE、INC

The incremental / Decrement is caused by the enable signal (CE) control . This interface is only available in ODELAY be in VARIABLE、VAR_LOAD or VAR_LOAD_PIPE Available in mode .

as long as CE Keep it high ,ODELAY On every clock Cycle increase or decrease TIDELAYRESOLUTION. INC The state of... Determines ODELAY Increasing or decreasing ; INC = 1 Increasing ,INC = 0 Decline , And clock Sync . If CE For low , No matter INC What's the state of , adopt ODELAY The delay will not change .

When CE Change to high level , Increasing / The decrement operation starts at the next positive clock cycle . When CE Turn to low power , Increasing / The decrement operation stops on the positive edge of the next clock .ODELAYE2 Programmable delay tap in primitive . When the delay tap ends （ Takeout 31）, Subsequent incrementing functions will return to the tap 0. The same applies to decreasing functions ： Decrease below zero and move to tap 31.

VAR_LOAD_PIPE The pipeline register function in mode is very useful in the design of bus structure . have access to LDPIPEEN once （ The Conduit ） Load a single delay , And then use LD p Update all delays to their new values at the same time .

ODELAY attribute

The following table summarizes ODELAY attribute

Attribute	Value	Default Value	Description
ODELAY_TYPE	String: FIXED, VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE	FIXED	Set the type of tapped delay line . FIXED Delay sets the static delay value . VAR_LOAD Dynamically load tap values . VARIABLE delay Dynamically adjust the delay value . VAR_LOAD_PIPE Be similar to VAR_LOAD Pattern , Be able to store CNTVALUEIN Value for future use .
ODELAY_VALUE	Integer: 0 to 31	0	Specify the number of fixed delay taps in fixed mode or the number of initial start taps in variable mode （ The output path ）. When ODELAY_TYPE Set to VAR_LOAD or VAR_LOAD_PIPE Mode time , This value is ignored and assumed to be all zero .
HIGH_PERFORMANCE_MODE	Boolean: FALSE or TRUE	FALSE	When it comes to TRUE when , This attribute reduces output jitter . Xilinx Power Estimator The tool quantifies the power difference .
SIGNAL_PATTERN	String: DATA, CLOCK	DATA	Make the timing analyzer consider the appropriate delay chain jitter in the data or clock path .
REFCLK_FREQUENCY	Real: 190–210, 290 to 310, or 390 to 410	200	Set the tap value used by the timing analyzer for static timing analysis （ With MHz In units of ）. 290.0 To 310.0 and 390 To 410 The range of is not available in all speed classes . Refer to the 7 series FPGA Data sheet .
CINVCTRL_SEL	Boolean: FALSE or TRUE	FALSE	Enable CINVCTRL_SEL Pins to switch dynamically C Polarity of pins .
PIPE_SEL	Boolean: FALSE or TRUE	FALSE	Select pipeline mode . Only when using VAR_LOAD_PIPE In operation mode , This attribute should only be set to TRUE.
DELAY_SRC	String: ODATAIN, CLKIN	ODATAIN	Select data input to ODELAY Source of module .

ODELAY_TYPE attribute

When set to FIXED when , The tap delay value is fixed as ODELAY_VALUE Property to set the number of taps determined . This value is the default , Cannot change after configuration .

When set to VARIABLE when , Select variable tap delay . Can be set by CE = 1 and INC = 1 To increase tap delay , Or by setting CE = 1 and INC = 0 To reduce tap delay . increase / Reduce operations and C Sync .

When set to VAR_LOAD or VAR_LOAD_PIPE when , Variable tap delay can be changed and dynamically loaded . Can be set by CE = 1 and INC = 1 To increase tap delay , Or by setting CE = 1 and INC = 0 To reduce tap delay . Increasing / Decrement operation and C Sync .VAR_LOAD Mode of LD Pin loading CNTVALUEIN The value displayed on . This allows the tap value to be set dynamically . stay VAR_LOAD_PIPE In mode ,LD Pin enables the current value in the pipeline register to be loaded into the output delay .

ODELAY_VALUE attribute

ODELAY_VALUE Property specifies the tap delay . The possible value is 0 To 31 Any integer between . The default value is 0. When set by LD When the signal reset tap is delayed , The value of tap delay reverts to ODELAY_VALUE. stay VAR_LOAD or VAR_LOAD_PIPE In mode , This property is assumed to be zero .

HIGH_PERFORMANCE_MODE attribute

When it comes to TRUE when , This attribute reduces output jitter . This reduction in jitter results in ODELAYE2 The power consumption of primitives increases slightly .

SIGNAL_PATTERN attribute

Clock and data signals have different electrical characteristics , So in ODELAY Different amounts of jitter accumulate in the chain . By setting SIGNAL_PATTERN attribute , The user enables the timing analyzer to properly consider jitter when calculating timing . The clock signal is periodic in nature , There is no continuous 1 or 0 Long sequence of , The data is random in nature , There can be long and short 1 and 0 Sequence .

ODELAY Pattern

When used as ODELAY when , Data input comes from IBUF or FPGA Logic , Output to ILOGICE2/ISERDESE2 or ILOGICE3/ISERDESE2. There are four operating modes available ：

• Fixed delay mode (ODELAY_TYPE = FIXED) ： In fixed delay mode , The delay value is preset as an attribute during configuration ODELAY_VALUE Determined number of taps . After the configuration , This value cannot be changed . When used in this mode ,IDELAYCTRL Primitives must be instantiated .

• Variable delay mode (ODELAY_TYPE = VARIABLE) ： In variable delay mode , The delay value can be configured by manipulating the control signal CE and INC To change . When used in this mode ,IDELAYCTRL Primitives must be instantiated .

The following table describes the VARIABLE Control pin used in mode .

C	LD	CE	INC	TAP Setting
0	x	x	x	No Change
1	1	x	x	ODELAY_VALUE
1	0	0	x	No Change
1	0	1	1	Current Value +1
1	0	1	0	Current Value –1
1	0	0	0	No Change

• Loadable variable delay mode (ODELAY_TYPE = VAR_LOAD)： Except that in this mode, there are (ODELAY_TYPE = VARIABLE) The same function ,ODELAY Taps can also be made from FPGA Logical 5 Input bit CNTVALUEIN< 4:0 > load . When LD When a pulse is generated , Appear in the CNTVALUEIN< 4:0 > The value at will be the new tap value . Because of this function ,ODELAY_VALUE Attribute ignored . When used in this mode ,IDELAYCTRL Primitives must be instantiated .

The following table describes what happens in VAR_LOAD Control pin used in mode .

C	LD	CE	INC	CNTVALUEIN	CNTVALUEOUT	TAP Setting
0	x	x	x	x	No Change	No Change
1	1	x	x	CNTVALUEIN	CNTVALUEIN	CNTVALUEIN
1	0	0	x	x	No Change	No Change
1	0	1	1	x	Current Value +1	Current Value +1
1	0	1	0	x	Current Value –1	Current Value –1
1	0	0	0	0	No Change	No Change

ODELAY sequential

The following table shows ODELAY Switching characteristics .

Symbol	Description
TIDELAYRESOLUTION	IDELAY tap resolution
TICECK/TICKCE	CE pin Setup/Hold with respect to C
TIINCCK/TICKINC	INC pin Setup/Hold with respect to C
TIRSTCK/TICKRST	LD pin Setup/Hold with respect to C

The image below shows ODELAYE2（ODELAY_TYPE = VARIABLE、ODELAY_VALUE = 0 and DELAY_SRC = CLKIN/ODATAIN） Sequence diagram .

Clock Events 1

stay C The rising edge of , Reset detected （LD High level ）, Result in output DATAOUT Select takeout 0 As 31 Output of the takeout chain .

Clock Events 2

stay C The rising edge of captures CE and INC Pulse on . This indicates an incremental operation . Output from tap 0 To the tap 1 Change without hair or thorns . After that, the text increases / Stability after decrement operation .

Clock Events 3

CE and INC No longer valid , To complete the incremental operation . The output remains at the tap indefinitely 1, until LD、CE or INC There is further activity on the pins .

The figure below shows the VAR_LOAD Mode of ODELAY Sequence diagram .

Clock Events 0

stay LD Before the pulse is generated , Tap setting and CNTVALUEOUT At unknown value .

Clock Events 1

stay C The rising edge of ,LD It is detected as high level , Result in output DATAOUT be equal to CNTINVALUE, And change the tap setting to tap 2. to update CNTVALUEOUT To represent the new tap value .

Clock Events 2

stay C The rising edge of captures CE and INC Pulse on . This indicates an incremental operation . Output from tap 2 To the tap 3 Change without hair or thorns .CNTVALUEOUT Updated to represent the new tap value .

Clock Events 3

stay C The rising edge of , One detected LD, Result in output DATAOUT be equal to CNTINVALUE. CNTVALUEOUT Displays the value of the tap setting . The output will remain at the tap indefinitely 10, until LD、CE or INC There is further activity on the pins .

Increasing / Stability after decrement operation

chart 2-26 Shows the response INC and CE Ordered ODELAY The line is tapped 0 Change to tap 1. obviously , When the tap 0 Data value and tap at 1 The data values at are different , The output must change state . however , When the tap 0 And taps 1 The data values at are the same （ for example , Both are 0 Or both 1） when , From the tap 0 To the tap 1 The conversion of does not result in output failure or interruption . By imagining that the transmitter data signal passes through ODELAY Takeout chain , This concept can be better understood . If the tap 0 And taps 1 Are near the center of the transmitted signal , Then tap 0 Data and taps at 1 There is no difference between the data at . under these circumstances , From the tap 0 To the tap 1 The conversion of does not cause the output to change . To ensure this ,ODELAY Increasing / The decrement operation is designed to be trouble free .

therefore , Users can access real-time user data through ODELAYE2 Primitives are dynamically adjusted in real time ODELAY Tap setting . As long as the current delay line value is close to the center of the transmitted data signal , These adjustments do not interrupt real-time user data .

When used in the clockticks path ODELAYE2 Primitives , Burr free behavior also applies . Adjusting the tap setting will not cause the output to fail or interrupt .

reference

1. UG471