Aurora8b10b IP usage-03-ip configuration application guide

Preface

This paper mainly aims at Aurora 8B/10B IP The related configuration items of the configuration interface are briefly described and introduced .

Custom configuration Aurora IP brief introduction

have access to Vivado Tool pair Aurora 8B/10B Kernel customization , To meet various requirements .

The following figure shows the customization IP The core Options tab of the interface , It includes Zynq-7000 and 7 Default options for series devices . The left side shows the currently configured Aurora 8B/10B A representative block diagram of the kernel . The right side contains user configurable parameters .

chart 4-2 Sum graph 4-3 Shows UltraScale The core Options tab of the device .

7 series Physical Layer

7 series Physical Layer The configurable options are as follows ：

Lane Width

Select the byte width of the transceiver used in the kernel . This parameter defines the... Of the transceiver TXDATA/RXDATA Width and user interface data bus width . Valid values are 2 and 4.
The default value is ：2

Line Rate

Line rate , stay 0.5 (Gb/s) To 6.6 (Gb/s) Enter the line rate value within the valid range of （ Gigabits / second ）. This value is the uncoded bit rate of data transmitted over the serial link . The total data rate of the kernel is （0.8 x Line rate ）x Aurora 8B/10B passageway .
The default value is ：3.125 Gb/s

GT REFCLK (MHz)

Select the reference clock frequency of the transceiver from the drop-down list . The reference clock frequency depends on the selected line rate . For best results , Please select the highest rate that can be actually applied to the reference clock input of the target device .

The default value is ：125.000 MHz

INIT clk (MHz)

Enter a valid... In the text box INIT clock frequency .
The default value is ：Zynq-7000 and 7 Series devices are 50 MHz,UltraScale The device is (line_rate/lane_width).

DRP clk (MHz)

Enter a valid... In the text box DRP clock frequency . UltraScale Device's INIT The clock and DRP Same clock frequency .
The default value is ：50 MHz

UltraScale series Physical Layer

comparison 7 series Physical Layer Configurable options ,UltraScale Configurable options add the following ：

Column Used

Select the appropriate... From the drop-down list GT Column .
The default value is ：Right

Lanes

Select the number of channels to use in the core . The valid range depends on the selected target device .

The default value is ：1

Starting GT Quad

Select the start of the start channel from the drop-down list GT Quad. The kernel is configured with a continuous number of channels , And select the channel selection option .

The default value is ：Quad X1Y0

Starting GT Lane

Select the starting channel of the kernel from the drop-down list . Use start Quad、 Channel and start channel , Generate a core with a continuous number of channels .

The default value is ：X1Y0

The kernel does not support cross SLR Boundary channel binding , And receive Vivado The limitation of .

GT Refclk Selection

Select from the drop-down list UltraScale Reference clock source of device transceiver .

The default value is ：Quad X1Y0 Of MGTREFCLK0

Generate Aurora without GT

This option is only available for UltraScale and UltraScale+ equipment . If you choose this option , Then it generates Aurora Kernel without GT, The sample design provides GT.

Link Layer

Dataflow Mode

choice Aurora 8B/10B Channel direction options supported by the kernel . Simplex Aurora 8B/10B The kernel has a one-way serial port , Can be connected to complementary simplex Aurora 8B/10B kernel . The available options are RX-only Simplex、TX-only Simplex and Duplex.

The default value is ：Duplex

Interface

Select the data path interface type for the kernel . Select framing to use... That allows you to encapsulate data frames of any length AXI4-Stream Interface . choice Streaming To use simple AXI4-Stream Interface by Aurora 8B/10B Channel streaming data .

The default value is ：Framing

Flow Control

Flow Control Select the desired options to add flow control to the core . User flow control (UFC) Allow applications to pass through Aurora 8B/10B The channel sends short high priority messages . Local flow control (NFC) Allow full duplex receivers to adjust the rate of data sent to them . The immediate mode allows you to insert idle code into the data frame , The completion mode only inserts idle code between complete data frames .

The options available are as follows ：

• None
• UFC
• Immediate NFC
• Completion NFC
• UFC + Immediate NFC
• UFC + Completion NFC

The default value is ： nothing

Back Channel

choice Back Channel The option is for simplex only Aurora kernel ; Duplex Aurora The kernel does not need this option .

The available options are ：

• Sidebands
• Timer

The default value is ：Sidebands

Use Scrambler/Descrambler

Use scrambler / descrambler Select to place 16 Bit scrambler / The descrambler contains to Aurora 8B/10B In design .

The default value is ： Not selected

Little Endian Support

Select to change all interfaces to little endian Format . By default , The core uses the big end format .

The default value is ： Not selected

Error Detection

Use CRC

Select to include... Of user data CRC. According to the channel width 2 or 4, The kernel implements CRC16 or CRC32.

Debug and Control

Additional Transceiver Control and Status Ports

Select to include transceiver control and status ports at the top of the core .

The default value is ： Not selected

Vivado Lab Tools

Select to place Vivado Lab tools added to Aurora 8B/10B kernel . This option provides a debugging interface , Can show Vivado Logic Analyzer Kernel status signals in .

The default value is ： Not selected

C_DOUBLE_GTRXRESET

This parameter can be customized IP When using TCL The console is set to 1. Enable this parameter to be used in the ppm Differences cause frequent buffer overflows / Assert additional reset in case of underflow . stay IP During hardware debugging , If in gt_reset_i Set it low and see RX Electrical idle exit condition , You can also set this parameter .

The default value is ：0（GUI Does not exist on ）

Shared Logic

The image below shows Customize IP Interface Shared Logic tab .

Select this option to open the IP The kernel or sample design contains the transceiver common PLL Its logic .

The available options ：

• Include sharing logic in the kernel
• Include shared logic in the sample design

Default ： Include shared logic in the sample design

The following figure shows the customization IP Interface GT Select the tab .

Column/Row Used

This option is only available for with more than one column / The row's device is visible . Select the appropriate column of the transceiver used from the drop-down list / That's ok . The columns used are only for Virtex-7 and Kintex-7 Device enabled , The lines used are only for Artix-7 Device enabled .

The default value is ：left/top

Lanes

Select the number of channels to use in the kernel （ Transceiver ）. The valid range is 1 To 16, Depends on the selected target device .
The default value is ：1

Lane Assignment

channel allocate , See the chart in the information area in the above figure . Two rows or four boxes represent a quadrilateral . Each active box represents an available transceiver . A tooltip is provided to specify which transceiver （ for example ,GTXE2_CHANNEL_X0Y0） Is being implemented in hardware .Aurora 8B/10B The kernel generates the transceiver layout incrementally (LOC) constraint . Lane numbers are used only to enable lanes and not to assign lane numbers .

GT Refclk1 and GT RefclK2
Core generation Click OK to generate the core . Aurora 8B/10B Modules in the kernel are written with the same name as the top level of the kernel Vivado Design tool project directory . of example_design Directory and file details , Please refer to No 80 The output of the page is generated .
notes ： 1. stay IP In the integrator ,Aurora 8B/10B The kernel follows IP The integrator guide sets the expected frequency values in long format ; however , Internal core accuracy and Vivado IDE Same as shown in .

2. Data and flow control ports are grouped into AXI4-Stream Interface . Other input and output ports are grouped into display interfaces .
3. For ports grouped in the display interface , The connection shall be made manually .

GT Refclk1 and GT RefclK2

Select... From the drop-down list in this section GTP、GTX or GTH Quad Reference clock source for .

The default value is ：

• GT REFCLK Source 1：GTPQn/GTXQn/GTHQn;
• GT REFCLK Source 2：None.

n The value of depends on the serial transceiver （GTX or GTH） The location of .

reference

1. PG046