[email protected] Abstract be based on UVM In the verification platform of , Register model i...">

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[UVM] don't say that your VIP can't use ral model

2022-06-23 00:40:00 MangoPapa

A general register model for accessing registers
[email protected]

Abstract

   be based on UVM In the verification platform of , Register model is often used (RAL Model) Equipment to be tested (DUT) Register access . The common method is to customize Adapter, Register model initiates register access request , the Adapter To Sequencer Identification of the Transaction, Send to Driver Read and write operations for register access on . For some general Sequencer And Driver, Its Transaction There is no concept of address data , Address required for register access operation 、 Data needs to be sent in multiple transactions , here Adapter Is no longer applicable . This paper adopts a new method , Rewrote uvm_reg_map Of do_bus_write、do_bus_read Mission , A stroke Transaction Split into multiple Transaction, Send multiple times , Can solve the above problems . The method used in this paper , Support Adapter + Non-Adapter Mixed mode .

key word :UVM、 Register model 、Adapter、 Universal interface 、JTAG



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