i. MX - rt1052 clock and phase locked loop (PLL) analysis

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Clock tree

RT1052 The clock distribution diagram of is like this ：

PLL PLL

• There are... In this chip 7 Phase locked loops
  

• PLL reference clock
  

ARM PLL (PLL1)

When it's time to PLL from 24 MHz When the reference clock synthesizes a low jitter clock , The PLL The clock output frequency range of is 650 MHz to 1.3 GHz. The output frequency is determined by 7 Bit register field CCM_ANALOG_PLL_ARM [DIV_SELECT] choice .

   Calculation formula ：

    PLL output frequency = Fref * DIV_SEL / 2

System PLL (PLL2)

The PLL from 24 MHz When the reference clock synthesizes a low jitter clock ,PLL It has an output clock , Plus 4 individual PFD（PFD0/1/2/3） Output .

PFD yes Phase Fractional Dividers Abbreviation , Phase fractional frequency division . In spite of this PLL It does have DIV_SELECT Register field , But it aims to make this PLL Only in 528 MHz Run at the default frequency （ That is, the frequency division value is only to meet the PLL stay 528 MHz Set for running under ）.

USB1 PLL (PLL3)

The PLL from 24 MHz When the reference clock synthesizes a low jitter clock ,USB1 PLL have 4 Frequency programmable PFD（ Phase fractional divider ） Output .
USB1 PLL The output frequency of is 480 MHz. Even if USB1 PLL have DIV_SELECT Register field , In normal operation , The PLL Should still always be set to 480 MHz.

Audio PLL (PLL4)

Audio PLL from 24 MHz When the reference clock synthesizes a low jitter clock , The PLL The clock output frequency range of is 650 MHz to 1.3 GHz. It has a fraction N Synthesizer .
Audio PLL You can choose / 1,/ 2,/ 4 These three post dividers. According to the following formula , Through to CCM_ANALOG_PLL_AUDIO and CCM_ANALOG_MISC2 The fields in the register set are programmed to set the output frequency .

   Calculation formula ：

    PLL output frequency = Fref * (DIV_SELECT + NUM / DENOM)

Video PLL (PLL5)

Video PLL from 24 MHz When the reference clock synthesizes a low jitter clock , The PLL The clock output frequency range of is 650 MHz to 1.3 GHz. It has a fraction N Synthesizer .
Video PLL You can choose / 1,/ 2,/ 4,/ 8,/ 16 These five post dividers. The following formula can be applied to CCM_ANALOG_PLL_VIDEO and CCM_ANALOG_MISC2 The fields in the register set are programmed to set the output frequency .

   Calculation formula ：

    PLL output frequency = Fref * (DIV_SELECT + NUM / DENOM)

Ethernet PLL (PLL6)

The PLL from 24 MHz When the reference clock synthesizes a low jitter clock , The PLL The reference clock generated is ：

• Make it first 500MHz Time base of

• By setting CCM_ANALOG_PLL_ENET [DIV_SELECT] Bit field will ref_enetpll1 It's programmed to 25、50、100 and 125 MHz
• ref_enetpll2 Fixed for 25 MHz

USB2 PLL (PLL7)

USB2 PLL By direct connection only USB UTM Interface to use .

Clock frequency reference