Verilog grammar basics HDL bits training 04

One 、Procedures:Always blocks

Use continuous assignment statements and always Block to implement and gate

• RTL Code

// synthesis verilog_input_version verilog_2001
module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
    assign out_assign = a & b;
    
    always @(*)
        out_alwaysblock = a&b;

endmodule

• Simulation oscillogram
  

Two 、Procedures:Always blocks(clocked)

Clock controlled always block

• RTL Code

// synthesis verilog_input_version verilog_2001
module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
	
    assign out_assign = a ^ b;
    always @(*)
        out_always_comb = a ^ b;
    always @(posedge clk)
        out_always_ff <= a ^ b;
    
endmodule

• Simulation oscillogram
  

3、 ... and 、Procedures:If statement

Build a two-way multiplexer

• RTL Code

// synthesis verilog_input_version verilog_2001
module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 

    assign out_assign = ({
    sel_b1,sel_b2} == 2'b11)? b : a;
    
    always @(*)
        if({
    sel_b1,sel_b2} == 2'b11)
            out_always = b;
    	else
            out_always = a;
endmodule

• Simulation oscillogram
  

Four 、Procedures:If statement latches

This is an example of a latch error , In general , Latches make us unwanted , So I'm writing if When the sentence is , To add else Statement guarantees that the output will not be latched

• RTL Code

// synthesis verilog_input_version verilog_2001
module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else
           shut_off_computer = 0;
    end

    always @(*) begin
        if (~arrived)
           keep_driving = ~gas_tank_empty;
        else if(arrived)
           keep_driving = 0;
        else
           keep_driving = gas_tank_empty;
    end

endmodule

• Simulation oscillogram

5、 ... and 、Procedures:Case statement

case Select statement

• RTL Code

// synthesis verilog_input_version verilog_2001
module top_module ( 
    input [2:0] sel, 
    input [3:0] data0,
    input [3:0] data1,
    input [3:0] data2,
    input [3:0] data3,
    input [3:0] data4,
    input [3:0] data5,
    output reg [3:0] out   );//

    [email protected](*) begin  // This is a combinational circuit
        case(sel)
            3'b000 : out = data0;
            3'b001 : out = data1;
            3'b010 : out = data2;
            3'b011 : out = data3;
            3'b100 : out = data4;
            3'b101 : out = data5;
            default : out = 0;
        endcase
    end

endmodule

• Simulation oscillogram

6、 ... and 、Procedures:Priority encoder

Build a priority encoder

• RTL Code

// synthesis verilog_input_version verilog_2001
module top_module (
    input [3:0] in,
    output reg [1:0] pos  );

    always @(*)begin
        case(in)
            in[0] : pos = 2'b0;
            in[1] : pos = 2'b1;
            in[2] : pos = 2'b2;
            in[3] : pos = 2'b3;
            default : pos = 2'b0;
        endcase
    end
        
endmodule

• Simulation oscillogram
  

7、 ... and 、Procedures:Priority encoder with casez

Use casez sentence

• RTL Code

// synthesis verilog_input_version verilog_2001
module top_module (
    input [7:0] in,
    output reg [2:0] pos  );

    always @(*)begin
        casez(in[7:0])
            8'bzzzz_zzz1 : pos = 3'b000;
            8'bzzzz_zz1z : pos = 3'b001;
            8'bzzzz_z1zz : pos = 3'b010;
            8'bzzzz_1zzz : pos = 3'b011;
            8'bzzz1_zzzz : pos = 3'b100;
            8'bzz1z_zzzz : pos = 3'b101;
            8'bz1zz_zzzz : pos = 3'b110;
            8'b1zzz_zzzz : pos = 3'b111;
            default : pos = 3'b000;
        endcase
    end
        
endmodule

• Simulation oscillogram

8、 ... and 、Procedures:Avoiding latches

• RTL Code

// synthesis verilog_input_version verilog_2001
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    
    always @(*)begin
        up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
        case(scancode)
            16'he06b : left = 1;
            16'he072 : down = 1;
            16'he074 : right = 1;
            16'he075 : up = 1;
        endcase
   	end
endmodule

• Simulation oscillogram