Vivado error code [drc pdcn-2721] resolution

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Not just solve error , More records and summaries . come on. ！

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Catalog

explain

Problem description

Solve mistakes

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explain

VIVADO IDE ：2021.1

operating system ：WIN 10

FPGA Chip family ：Kintex 7 (xc7k410tffg900-2L)

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Problem description

Recently, I was debugging a signal processing board , Onboard chip is XILINX Of 7 series FPGA（xc7k410tffg900-2L）.MGT BANK The reference clock for is 156.25MHz The differential clock , By CDCM6208 Output driver of clock chip .CDCM6208 When the configuration is complete , The first task is to verify the 156.26MHz Does the differential clock really enter FPGA Of MGT BANK. The specific verification steps are as follows ：

First step ： Use The original language IBUFDS_GTE2 take MGT BANK The differential reference clock of is introduced and converted to Single ended clock of the same frequency .

  Instantiate in the code ：

   IBUFDS_GTE2 #(
      .CLKCM_CFG("TRUE"),   // Refer to Transceiver User Guide
      .CLKRCV_TRST("TRUE"), // Refer to Transceiver User Guide
      .CLKSWING_CFG(2'b11)  // Refer to Transceiver User Guide
   )
   IBUFDS_GTE2_inst (
      .O(O_CLK_156M25),         //  Output 156.25M Single ended clock 
      .ODIV2(),                 //  The port can be idle 
      .CEB(1'b0),               //  The low level input of this port is valid   Always give  0 
      .I (I_CLK_156M25_P),      // BANK  Reference clock   Input port  P
      .IB(I_CLK_156M25_N)       // BANK  Reference clock   Input port  N
   );

The second step ： Send the single ended clock output by the primitive into MMCM perhaps PLL Frequency division , For system design

That's probably the problem , If you don't go in MMCM perhaps PLL, There may be no errors

  clk_wiz_1 instance_name1
   (
    // Clock out ports
    .clk_out1(CLK_10M),     // output clk_out1
    // Status and control signals
    .reset(0), // input reset
    .locked(locked),       // output locked
   // Clock in ports
    .clk_in1(O_CLK_156M25));      // input clk_in1

Then in the process of implementation, it will report DRC Error of , Against the design rules （Design Rule）:

[DRC PDCN-2721] IBUFDS_GT_loads_clock_region: IBUFDS_GTE2 IBUFDS_GTE2_inst drives MMCME2_ADV instance_name1/inst/mmcm_adv_inst in a different clock region and must do so using local routing resources which may negatively affect clock performance. Use CLOCK_DEDICATED_ROUTE set to FALSE to indicate this is intended.

The general reason for the mistake is IBUFDS_GTE2 Primitive out of the clock area and driven by MMCM or PLL The clock area of is inconsistent . Be careful , Personally, I think the concept of clock area here is the area of clock resource distribution on the physical level , Different from STA（ Static time series analysis ） The concept of clock domain .

Solve mistakes

In fact, the solution has been given at the end of the error . Need to be in XDC The following constraints are made in the document ：

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets O_CLK_156M25]

Then the bit stream can be generated without error ~

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The above is right and wrong   [DRC PDCN-2721]  The record of , Welcome to leave a message , Add ~

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