Analysis and solution of data and clock mismatch delay in SPI transmission

Hardware environment

        4G modular ：FIBOCOM_AL940, be based on MDM9628 CordX-A7 1.3 GHz Single core ,RAM 70M ROM 150M, Contains two groups spi Interface , Only the main equipment , The biggest support 50M Clock speed ;

        MCU Single chip microcomputer ：RH850/F1K, Contains two groups spi Interface , Support master-slave mode ; Maximum support from mode 5M Clock speed ;

        4G Module power domain 1.8V, Single chip microcomputer 3.3V Power domain , In the middle TXS0104E and TXS0108E Chip conversion level ;

        4G Module dominated mode , Single chip microcomputer as slave device , But the single-chip computer sends data to 4G modular ;

Problem description

        At the clock rate 2.4 The following data is sent normally ：0xaa 0x55

          stay 3.2M The second byte data does not match the clock , A clock is shifted backward bit position , the last one bit The high and low bits will not be changed when the clock is idle ：

          Through direct connection of data line and clock line ,3.5M Normal rate , But a lot of data will be lost , The single chip microcomputer did not send data

        The clock is 4.8M when , The clock shifts back one to three random occurrences . 

  Problem analysis

        1、 It is suspected that the mode set by the level conversion chip is incorrect, resulting in the problem of maximum data rate , modify spi Of 4 There is no improvement in these modes ;

        2、 Suspect the up and down resistance of the clock and data line , No improvement after modification attempt ;

        3、 The suspicion is 4G Problems caused by module data sampling , Disconnect the data line and measure the data pin at the MCU end , No improvement ;

        4、 doubt 4G Module clock chip is not standard, resulting in , And IMX8 Compare the clock of , There are subtle differences , But the waveform meets the requirements of the manual ;

         5、 SCM and IMX8 The connection is normal , All are 3.3V There is no level conversion , The communication procedure is 4G Module communication is abnormal , The MCU development engineer said that the program had not been changed , So it's not a software problem , The results are only compared spi Code , When comparing the clock code of single chip microcomputer, we found an exception , There are differences in frequency doubling settings ,4G The module defaults to EMCLK,IMX8 Use PPLLOUT, This leads to the difference of frequency doubling ： 

Problem solving

        The single chip microcomputer selects the clock source as PPLLOUT after , Data transmission is normal ,5M The speed is also normal , However, the following tests still have different degrees of packet loss probability .

The problem summary

        Involving hardware engineers ,BSP The engineer , MCU Engineer ,4G modular spi Drive development engineer , SCM technical support , Finally, it was found that it was a problem of setting , It took weeks to put this simple spi Problem solving , It's really shameful .