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[digital ic/fpga] detect the position of the last matching sequence
2022-06-27 23:52:00 【FPGA silicon agriculture】
Title Description
Write a module , Enter a 64 Bit stream of bits , Identify and match out 101101 The last position of , And output position information .
Code
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2022/06/21 10:34:41
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top(
input logic clk,
input logic rst,
input logic valid,
input logic din,
output logic done,
output logic [5:0] pos
);
//101101
logic [5:0] shift_reg;
logic [5:0] cnt;
//cnt
[email protected](posedge clk,posedge rst)
if(rst)
cnt<=0;
else if(valid)
begin
if(cnt==64-1)
cnt<=0;
else
cnt<=cnt+1;
end
//shift_reg
[email protected](posedge clk,posedge rst)
if(rst)
shift_reg<=0;
else if(valid)
shift_reg<={
shift_reg[4:0],din}; // High order input first
//pos
[email protected](posedge clk,posedge rst)
if(rst)
begin
pos<=64;
end
else if(shift_reg==6'b101101)
begin
pos<=cnt-6;
end
//done
[email protected](posedge clk,posedge rst)
if(rst)
done<=0;
else
done<=(cnt==64-1&&valid)?1:0;
endmodule
Test platform
module test;
logic clk;
logic rst;
logic valid;
logic din;
logic done;
logic [5:0] cnt;
logic [5:0] pos;
logic [63:0] data;
//
initial
begin
//data={12'b101101101101,52'd0};
data={
20'd0,12'b101101101101,32'd0};
end
//clk
initial
begin
clk=0;
forever
#5 clk=~clk;
end
//rst
initial
begin
rst=1;
#100
rst=0;
end
//valid,din
initial
begin
valid<=0;
cnt<=0;
wait(rst==1'b0);
@(posedge clk);
repeat(64)
begin
valid<=1;
din<=data[63-cnt];
cnt<=cnt+1;
@(posedge clk);
end
valid<=0;
end
top U(.*);
/* input logic clk, input logic rst, input logic valid, input logic din, output logic done, output logic [5:0] pos ); */
endmodule
result
Input bitstream is data={20’d0,12’b101101101101,32’d0}, therefore , The position of the last matching sequence should be 20+6=26, In line with expectations .
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