Xilinx FPGA one way clock input two PLLs

Xilinx FPGA One clock input two PLL

Implementation method ：

1、 The clock is input by the global clock input pin .

2、 The input clock first enters IBUFG + BUFG, Then output a global clock

3、 Input the output global clock into two PLL,PLL Configuration input is No Buffer, Output is BUFG/BUFGCE etc.

The code is as follows ：

     wire    O   ;
    IBUFG  IBUFG_inst (
      .O(O),     // Buffer output
      .I(i_sys_clk_50m)      // Buffer input (connect directly to top-level port)
       );
    wire O1;
    BUFG BUFG_inst(
    .O(O1), // 1-bit output: Clock output
    .I(O)  // 1-bit input: Clock input
    );
   
   
    PLL PLL_INST(
    // Clock out ports
     .sys_clk_10m    	(        )
    ,.sys_clk_20_46m    (     )
    ,.sys_clk_50m       (        )
    ,.sys_clk_100m      (       )
    // Status and control signals 
    ,.reset             ( 0                 )    
    ,.sys_rst_n         ( sys_rst_n         )
    // Clock in ports
    ,.clk_in1           ( O1     )
    );
    
    wire    clk_10m ;
    wire    clk_100m ;
    wire    clk_50m1 ;
    wire    clk_50m2 ;
    wire    clk_50m3 ;
    wire    clk_50m4 ;
    wire    rst_n1    ;
    
    wire    clk_10m_ce  ;
    wire    clk_100m_ce  ;
    wire    clk_50m1_ce  ;
    wire    clk_50m2_ce  ;
    wire    clk_50m3_ce  ;
    wire    clk_50m4_ce  ;
    
    reg     [15:0]  cnt111;
    reg             flag111;
    wire            w_flag  ;
    assign w_flag = flag111 ;
    
//    assign clk_100m_ce = flag111 ? 
    clk_wiz_1 clk_wiz_1_inst(
  // Clock out ports  
    .clk_10m_ce(1),
    .clk_10m(sys_clk_10m),
    .clk_100m_ce(rst_n1),
    .clk_100m(sys_clk_100m),
    .clk_50m1_ce(1),//
    .clk_50m1(sys_clk_50m),
    .clk_50m2_ce(flag111),
    .clk_50m2(clk_50m2),
    .clk_50m3_ce(flag111),
    .clk_50m3(clk_50m3),
    .clk_50m4_ce(flag111),
    .clk_50m4(clk_50m4),
  // Status and control signals               
    .reset(0), 
    .locked(rst_n1),
 // Clock in ports
    .clk_in1(O1)
  );