FPGA systematic learning notes serialization_ Day8 [design of 4-bit multiplier and 4-bit divider]

FPGA Systematic study notes serial _Day8【4 Bit multiplier 、4 Bit divider design 】 【 Principle and verilog Realization 、 Simulation 】 piece

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Serial 《 Three core smart fpga Design and development - The first 8 God 》 【4 Bit multiplier 、4 Bit divider design 】 【 Principle and verilog Realization 、 Simulation 】

Original author ： Zifeng River Please contact the group owner for authorization , Otherwise, we will be held responsible

One 、 Principle of multiplier

1、 Let's first look at the multiplication process of the decimal system

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You can see it , We are using the bits of the multiplier separately 、 ten 、 The hundreds are multiplied by the multiplicand to get ;

The final result be equal to A + B10 + C100 = 401050

2、 Binary multiplication process

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You can see it , Binary multiplication is the same as decimal

The final result be equal to A + B2 + C4 + D*8 = 1991

Two 、verilog Code implementation

mult4bit.v

module mult4bit(
    input   [3:0]       a,
    input   [3:0]       b,
     
    output  [7:0]       y
);
 
    wire    [7:0]   temp1;
    wire        [7:0]       temp2;
    wire        [7:0]       temp3;
    wire        [7:0]       temp4;
 
    assign temp1 = {4'b0000,a&{4{b[0]}}};
    assign temp2 = {3'b000,a&{4{b[1]}},1'b0};
    assign temp3 = {2'b00,a&{4{b[2]}},2'b0};
    assign temp4 = {1'b0,a&{4{b[3]}},3'b0};
     
    assign y = temp1 + temp2 + temp3 + temp4;
 
endmodule

3、 ... and 、 Write simulation scripts

mult4bit.v

`timescale 1ns/1ps
 
module mult4bit_tb();
 
    reg     [3:0]       a;
    reg     [3:0]       b;
     
    wire    [7:0]       y;
 
    mult4bit mult4bit_inst(
        .a      (a),
        .b      (b),
         
        .y      (y)
    );
 
    initial begin
        repeat (100)begin
            a = {$random}%16;
            b = {$random}%16;  
            #20;
        end
    end
 
endmodule

Four 、 Simulation results

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Simulation results show that our multiplier design is correct

5、 ... and 、 The principle of the divider

1、 Let's first look at the division process of the decimal system

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Division from decimal , We can see that there are several steps ;

1.1、 First, division is done from high to low ;

1.2、 Each one should add the remainder left by the previous one , Make a new number and divisor comparison ;

1.3、 When the new number is greater than / When it's equal to the divisor , Write quotient for surplus ;

1.4、 Proceed in the above manner , Until the end of the divisor , Division is over .

2、 Binary division process

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As you can see from the figure, binary division , It's in line with the decimal system

6、 ... and 、 Code implementation

div4bit.v

module div4bit(
    input   [3:0]       a,
    input       [3:0]       b,
     
    output  [3:0]       s,
    output  [3:0]       y
 
);
 
    wire    [3:0]   part1;
    wire    [3:0]   part2;
    wire    [3:0]   part3;
    wire    [3:0]   part4;
     
    assign s[3]     = (a[3] >= b)?1'b1:1'b0;
    assign part1    = (a[3] >= b)?(a[3]-b):a[3];
     
    assign s[2] = ({part1[0],a[2]} >= b)?1'b1:1'b0;
    assign part2 = ({part1[0],a[2]} >= b)?({part1[0],a[2]}-b):{part1[0],a[2]};
     
    assign s[1] = ({part2[1:0],a[1]} >= b)?1'b1:1'b0;
    assign part3 = ({part2[1:0],a[1]} >= b)?({part2[1:0],a[1]}-b):{part2[1:0],a[1]};
 
    assign s[0] = ({part3[2:0],a[0]} >= b)?1'b1:1'b0;
    assign part4 = ({part3[2:0],a[0]} >= b)?({part3[2:0],a[0]}-b):{part3[2:0],a[0]};
 
    assign y = part4;
 
// This code is also executed correctly , But the compiler will warn , Because we put 5bit Data assigned to 4bit
 
//  assign s[3] = a[3] >= b;
//  assign part1 = (s[3]) ? a[3] - b : a[3];
// 
//  assign s[2] = {part1,a[2]} >= b;
//  assign part2 = (s[2]) ? {part1,a[2]} - b : {part1,a[2]};
// 
//  assign s[1] = {part2,a[1]} >= b;
//  assign part3 = (s[1]) ? {part2,a[1]} - b : {part2,a[1]};
// 
//  assign s[0] = {part3,a[0]} >= b;
//  assign part4 = (s[0]) ? {part3,a[0]} - b : {part3,a[0]};
// 
//  assign y = part4;
     
endmodule

7、 ... and 、 Write simulation files

div4bit_tb.v

`timescale 1ns/1ps
 
 
module div4bit_tb();
        reg     [3:0]       a;
        reg [3:0]       b;
         
        wire    [3:0]       s;
        wire    [3:0]       y;
 
        div4bit div4bit_isnt(
            .a      (a),
            .b      (b),
             
            .s      (s),
            .y      (y)
        );
 
        initial begin
            repeat(100)begin
                a ={$random}%16;
                b ={$random}%16;
                #20;
            end
         
        end
 
endmodule

8、 ... and 、 Simulation results

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It can be seen from the simulation results that , We designed 4bit The divider is correct .