CPU design (single cycle and pipeline)

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obtain CPU Design source file （ Do not look at single cycle and pipeline ）

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Functional description of the design ( Contains a description of all the implemented instructions , And single cycle / Assembly line CPU frequency )

add: Read the operands in the two registers containing operands specified in the instruction , Then add and write the result to the destination register .

sub: Read the operands in the two registers containing operands specified in the instruction , Then write the result to the destination register after subtracting .

and: Read the operands in the two registers containing operands specified in the instruction , Then write the result to the destination register after the and operation .

or: Read the operands in the two registers containing operands specified in the instruction , Then write the result to the destination register after the or operation .

xor: Read the operands in the two registers containing operands specified in the instruction , Then write the result to the destination register after XOR operation .

sll: Read the operands in the two registers containing operands specified in the instruction , And then I'll put the operands 1 Logical shift left operand 2 Write the result to the destination register after the number of bits of size .

srl: Read the operands in the two registers containing operands specified in the instruction , And then I'll put the operands 1 Logical shift right operand 2 Write the result to the destination register after the number of bits of size .

sra: Read the operands in the two registers containing operands specified in the instruction , And then I'll put the operands 1 Arithmetic shift right operand 2 Write the result to the destination register after the number of bits of size .

addi: Read out the operands in one of the registers containing operands specified in the instruction , Then add the operand to the immediate value specified in the instruction and write the result to the destination register .

andi: Read the operand from a register containing the operand specified in the instruction , Then the operand is summed with the immediate value specified in the instruction, and the result is written into the destination register .

ori: Read the operand from a register containing the operand specified in the instruction , Then the operand is or computed with the immediate value specified in the instruction, and the result is written to the destination register .

xori: Read the operand from a register containing the operand specified in the instruction , Then XOR the operand with the immediate number specified in the instruction and write the result to the destination register .

slli: Read the operand from a register containing the operand specified in the instruction , Then, the operand is logically shifted left by the number of bits of the size of the immediate specified in the instruction, and the result is written to the destination register .

srli: Read the operand from a register containing the operand specified in the instruction , Then, the operand is logically shifted to the right by the number of bits of the size of the immediate specified in the instruction, and the result is written to the destination register .

srai: Read the operand from a register containing the operand specified in the instruction , Then, the operand is arithmetically shifted right by the number of bits of the size of the immediate specified in the instruction, and the result is written to the destination register .

lw: Add the operand in the register containing the operand specified in the instruction to the immediate value specified in the instruction , Then read out the value of the storage unit whose address is the result of the addition , And write it to the destination register .

ialr: Add the operand in the register containing the operand specified in the instruction to the immediate value specified in the instruction as the next PC Value , And then put the current PC The value of the add 4 The resulting value is written to the destination register .

sw: The register containing the operand specified in the instruction 1 The operands in and the immediate values specified in the instruction are added , Then, the register containing the operand specified in the instruction 2 The operands in are written to the storage unit with the addition result as the address .

beq: Read the operands in the two registers containing operands specified in the instruction , And then compare them , If operand 1 And operands 2 equal , The current PC The address plus the immediate number specified in the instruction is the result of the next PC Value , otherwise , Just put the current PC Add... To the address 4 As the result of the next PC Value .

bne: Read the operands in the two registers containing operands specified in the instruction , And then compare them , If operand 1 And operands 2 It's not equal , The current PC The address plus the immediate number specified in the instruction is the result of the next PC Value , otherwise , Just put the current PC Add... To the address 4 As the result of the next PC Value .

blt: Read the operands in the two registers containing operands specified in the instruction , Then make a signed comparison , If operand 1 Less than operand 2, The current PC The address plus the immediate number specified in the instruction is the result of the next PC Value , otherwise , Just put the current PC Add... To the address 4 As the result of the next PC Value .

bge: Read the operands in the two registers containing operands specified in the instruction , Then make a signed comparison , If operand 1 Greater than or equal to the operand 2, The current PC The address plus the immediate number specified in the instruction is the result of the next PC Value , otherwise , Just put the current PC Add... To the address 4 As the result of the next PC Value .

lui: The immediate number specified in the instruction is expanded into 32 The result after bit is written to the destination register .

jal: Will the current PC The value of is added to the immediate value specified in the instruction as the next PC Value , And then put the current PC The value of the add 4 The resulting value is written to the destination register .

One cycle CPU frequency 25MHz
Assembly line CPU frequency 90MHz

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Single cycle module function

PC: Pass the address value of the next instruction to imem modular .

Next. _pc: Get the next - Time of pc Value and pass to PC modular .

imem: A module that stores instructions .

decoder: Decoding unit , Split the input instruction , Get the corresponding operand or immediately after symbol expansion , For later modules .

control: Through the input instructions, the corresponding values of each control signal are obtained and output to other modules .

execute: The corresponding operands are calculated and the results are output to the required modules .

dram: Storage unit .

compare: Perform the comparison operation of the comparison instruction , And output a signal to decide whether to jump .

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Pipeline module functions

PC: Pass the address value of the next instruction to irom modular .

Next_pc: Get the next pc Value and pass to PC modular .

irom: A module that stores instructions .

jump_ test: Detect whether it is a jump instruction , And decide whether to pause .

IF_ID_ reg: take IF Part of the signal of the phase is transmitted to ID Stage .

decoder: Decoding unit , Split the input instruction , Get the corresponding operand or immediately after symbol expansion , For later modules .

control: Through the input instructions, the corresponding values of each control signal are obtained and output to other modules .

conf_ test: Conflict detection module , Detect whether there are data conflicts , And output the corresponding conflict signal and the correct value that should be read out from the register after the conflict .

ID_ EX_ reg: take ID Part of the signal of the phase is transmitted to EX Stage .

execute: The corresponding operands are calculated and the results are output to the required modules .

compare: Perform the comparison operation of the comparison instruction , And output a signal to decide whether to jump .

EX_MEM_reg: take EX Part of the signal of the phase is transmitted to MEM Stage .

dram: Storage unit .

MEM_WB._reg: take MEM Part of the signal of the phase is transmitted to WB Stage .

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Pipeline Division

IF Stage : Finish next time pc Calculation of values , And according to the present pc Value to change the corresponding instruction from irom Take it out of the module and output it to the subsequent stages ; Furthermore, there is the detection of jump instructions , Decide whether to pause .

ID Stage : receive IF Instructions obtained in the phase , Then the effective information in the instruction is extracted , for example I The immediate sign extension value of a type instruction 、R The operands of type instruction, etc , And get the value of each control signal, and then output it to the subsequent modules , Furthermore, check whether there is data conflict , And deal with it accordingly .

EX Stage : receive ID Some control signals and corresponding operands from the stage , And carry out corresponding calculation or comparison operation accordingly , Output the result to MEM Stage .

MEM Stage : Yes DRAM Read or write .

WB Stage : The data obtained in the previous stage is selected according to the control signal and written into the corresponding register .