About SDRAM memory

One 、 Yes SDRAM A preliminary understanding of

1.1 What is? SDRAM

SDRAM（Synchronous Dynamic Random Access Memory）, Synchronous dynamic random Access memory .

Sync ： The operating frequency is the same as the system clock frequency of the corresponding controller , And the command and data transmission inside the memory are based on this

dynamic ：SDRAM Use capacitors to store data , Power down, data loss , Therefore, the storage sequence needs to be refreshed continuously to ensure that the data is not lost

Random ： Data is not stored linearly （fifo）, The address can be randomly assigned for reading and writing .

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1.2 SDRAM Row and column address of

First, a bit data access circuit is given as follows ：

To read this bit of data , We need to open the row address first （ Activate /active）, Then open the column address , Then the level state of the capacitor can be displayed in data_bit On , Thus, one bit data reading is realized . Or say , The level state on the data line is sent to the capacitor , Write one bit data .

There is a time interval between opening the row address and being able to open the column address ——tRCD（ Different devices , The value is also different ）
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Column address open , To the data presented in data_bit There is also a certain clock delay on the , It is called column gating latency （CL）

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From this we can get SDRAM A simplified model of internal row and column addresses , Each of these rows , Show only 1bit The data of .
When we specify row and column address lines , You can get the corresponding storage unit .

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Specify the line address as shown in the figure =3, Column address =5, You can find the storage unit in the corresponding black area .

The storage unit in the above figure can store a width of 8/16/32 The data of . For the whole row and column block , be called Logic Bank（L-Bank）.

If a Bank May cause addressing conflicts , So most of them SDRAM The interior is 4 A logic bank Design , Data reading and writing process ：

Specify logic Blank Address —— Specify the line address —— Specify the column address —— Determine the addressable storage unit .

Be careful ： Only one at a time Bank A storage unit of the .

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1.3 SDRAM Calculation of capacity

The capacity of a storage unit is equal to the bit width of the data bus , The unit is bit. So in general SDRAM storage capacity ：

SDRAM Total storage capacity = L-Bank The number of × Row number × Number of columns × The capacity of the storage unit

if SDRAM Line address of 13bit, Column address 9bit,4 individual bank,16bit data , be

SDRAM Capacity = 4 × 2^13 × 2^9 × 16 = 268435456 bit / 8 = 33554432 (B )= 33554432 / 1024 (KB) = 32768 /1024 MB = 32MB

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1.4 SDRAM Pins and definitions

x4 - x16： respectively 4、8、16 A wide
#： Indicates that the low level is active ;
— ： Express x8 and x4 Pin function and x16 The pin functions are the same .

The definition is as follows ：
CLK：SDRAM Working clock , The rising edge of the clock performs input sampling
BAn[1:0]：Bank Address line
DQn [15:0]： Two way data bus
An[12：0]： Address line , When you choose a Bank Line address of , Want to use A0-A11; When you choose an address , use A0-A8,A10 Signals can be used to control Auto-precharge Automatic pre charging

Learn from the boss SDRAM

1.5 SDRAM Internal structure block diagram

Usually SDRAM There are four Bank, Such as Bank0 ~ Bank3;
For addressing and other functions , There is also a series of controllers inside , Command decoder （ Operate the memory module by sending the command , The command operation is as follows ：SDRAM Initialization and read / write commands ）、 Logic control unit 、 Address register 、 Data register etc. .

In detail ： Outside through CS_N、RAC_N、CAS_N、WE_N These four signals constitute the command signal and the address bus （ Chip selection signal determination bank, Row column strobe signal gives row column address ,WE Give write enable ）, Then the command goes through Command decoder After decoding , Save the control parameters in the mode register , The logic control unit can control the logic operation .

Two 、SDRAM Operation command

The basic operation command is as follows ：

#： Indicates that the low level is active
NOP： Empty operation
Precharge ： Is to write the data back to the capacitance , So open the row address , To ensure that the data is not lost in the next read

2.1 An empty command

Regardless of SDRAM In what state , This command can be written Enter into , This command can be given to the selected SDRAM Pass an empty operation , The purpose is to prevent SDRAM When idle or waiting , Other commands are written . As shown in the first two , Not selected bank And check bank, But without giving row and column and writing enable , All for NOP command .

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2.2 Load mode register command

1、 In the internal structure diagram, we can see mode register , stay SDRAM During power on initialization （ be-all Bank Are idle ）, After executing the configuration mode register command ,SDRAM You must wait for the corresponding response time tMRD(Register Set Cycle) after , To execute a new command .

2、 The mode register command passes through the address bus A0-A11 To configure , Different assignments correspond to different modes of register configuration , Unused address bus A12 Set to low level , At the same time, the mode register will always store the configuration information , Until the next programming or power failure .

The following is the mode register address bus definition A12-A0 ：

A0-A2 Control burst length ,Brust Length：

Burst is the continuous transmission of data between adjacent storage units in the same row , The continuous data volume is the burst length BL.

The typical burst mode is 1,2,4,8,Full Page, Full page burst transmission refers to logic Bank The transfer of all storage units in a row from beginning to end , Therefore, a full page can transmit a whole row of data at a time .

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A3 Control burst type ,BT：

A3 = 0： Sequential burst ;A3 = 1： Interlaced burst

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A6,A5,A4 Control column gating latency ,CAS Latency

The read command is registered , To The time interval at which data appears on the data bus is called the column gating latency , Can be set to 2 or 3 Clock cycles

You can see , After the read command is given , stay T2 The first valid data appears on the data bus , therefore CL = 2;

Empathy , Upper figure CL = 3 ;

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A7,A8 Control operation mode ,Operating Mode

SDRAM There are standard patterns 、 Test mode and other modes ,{A7,A8} = {0,0} , Enter standard mode ..

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A9 Control write mode ,WB

When A9 =0,SDRAM Of read / Writing is done in burst mode The way , The burst length is determined by the burst length register (A0-A2) Set up ;
When A9 =1 when , SDRAM Of Read using burst , The burst length is determined by the burst length register (A0-A2) Set up , but Write without using burst mode , Each write command can only write one data .

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A10-A12 reserved ,Reserver

Configuration of mode register has no effect , The assignment is 0 that will do .

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Explanation of the order ：

Activate command （active）

Control the activation command {CS_N,RAS_N,CAS_N,WE_N} = 4‘b0011.

The activation command is used to open a specific Bank（ from BA0 and BA1 decision ） And the specified line （ from A0-A12 decision ）.
The line remains active and can be read and written , When a precharge command is executed , The line is closed .

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Read command （read）

Control the activation command {CS_N,RAS_N,CAS_N,WE_N} = 4‘b0101.
specific Bank（ from BA0 and BA1 decision ） And the specified column （ from A0-A9 decision ,A10 Controls whether the precharge operation is automatically performed immediately after the burst read is completed , Low means no execution ）
The read command is used to start a burst read operation on an activated line

The picture above shows , When the read command appears , after 2 individual clk After the column gating latency of , The first valid data appears on the data bus , The burst write length is specified as 4, So I wrote n~n+3, Because when the second read command appears , Also in 2 individual clk after , The first valid data can appear on the data bus b……

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Write orders （write）

Control the activation command {CS_N,RAS_N,CAS_N,WE_N} = 4‘b0100.
The write command is used to initiate a burst write operation on an active line .（A10 Controls whether the precharge operation is automatically performed immediately after the burst write is completed , Low level does not execute ）

You can see , Write burst length is 2, So when the write command appears , Also specify the corresponding bank And column , Therefore, data can be written to the data bus at this time .

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Pre charge command (Precharge)

Control the activation command {CS_N,RAS_N,CAS_N,WE_N} = 4‘b0010.

The precharge command turns off the specified bank Or all bank（ Single or all bank from A10 decision , A high level indicates that all bank Line precharge , Low level indicates that the specified bank Precharge the rows in ）

After the order is executed , Must wait for the corresponding **tRP（** Precharge command cycle ）, Corresponding Bank Can be operated again .

The precharge command is in the initialization process 、 Automatic refresh and read / write operations will be used .

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Automatic precharge command (Auto Precharge)
Without adding additional execution instructions , Achieve the same effect as the precharge command . This function is for SDRAM When issuing a read / write command , Use A10 Indicate that it is
No immediately after the burst read / write is completed Automatically perform precharge operation To achieve

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Burst termination command （BURST TERMINATE）

Control the activation command {CS_N,RAS_N,CAS_N,WE_N} = 4‘b0110.

The burst interrupt command is used to truncate bursts of fixed length or full page length .（ The row will not be closed , It just interrupts ）

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Auto refresh command (Auto Refresh)

SDRAM Power down, data loss , Only through the refresh operation can the reliability of the data be guaranteed . Refresh includes automatic refresh and self refresh . After sending the order CKE When the clock is valid , Use automatic refresh operation , Otherwise, use self refresh （ Self renewal ） operation （ It is mainly used for data saving in sleep mode and low power consumption ）.

SDRAM The refresh operation of is periodic , Data related operations can be performed between two refreshes . We looked at SDRAM Chip parameters , I often see 4096 Refresh Cycles/64ms The logo of , there 4096 It means every... In the chip Bank The number of rows .

The refresh command is only valid for one line at a time , That is to say 64ms The inner chip needs to be completed 4096 Refresh operation , So on average 15.625μs Refresh once , You can also refresh all at once , It depends on the timing of your data reading and writing .

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** Data mask **

A data mask is used to mask unwanted data , When the burst length is 4 When , Description continuous transmission 4bit data , If the second bit Data doesn't need to be , Then we can use the data mask DQM technology , Every DQM The signal line corresponds to a byte , adopt DQM, Memory can be controlled I/O The port cancels input or output data .

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3、 ... and 、SDRAM Power on initialization

SDRAM If the chip wants to work normally , It must be carried out after power on Initialization operation , Otherwise, it cannot be used normally .
The following is the initialization process ：

Wait for at least after power on 100us, General direct 200us, Give empty command operation during waiting .（ Different chips have different time ）
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Time delay 200us after , For all bank Precharge , This closes all bank All of the line （A10 High level ）, Make all bank Enter the idle state
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After entering the idle state , At least two cycles of automatic refresh commands are required , After completion , Load mode register command

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Analyze initialization timing ：

About waiting time ：

tRP： The time to wait after issuing the precharge command , It's usually 2 individual clk
tRFC： The time to wait after issuing the automatic refresh command , It's usually 7 individual clk
tMRD： Time to wait after sending the set mode register command , It's usually 3 individual clk

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Through the sequence diagram , We summarize initialization as follows ：
1、 First power on and CKE Set to low , wait for 100us, meanwhile stay 100us At some point in time CKE The signal goes high , meanwhile Send an empty command （ Prevent right SDRAM Misoperation occurs ）.
2、 the second clk,A10 pull up , For all the Bank Conduct Precharge .
3、 Wait after pre charging tRP Time , Empty commands are still sent during this period .
4、 after tRP After time , In the 3 individual clk, Enter into Auto refresh command , after tRFC Time , This process also sends an empty command .
5、 after tRFC After time , Perform the automatic refresh operation again （ Different chips have different refresh times , At least two. clk Automatic refresh command for ）.
6、 Repeat auto refresh and go through tRFC after , Enter into Load mode register command , Address bit A0-11 To write the value of the mode register .
7、 wait for tMRD Time , And send an empty command during ,tMRD After time ACTIVE,—— SDRAM Initialization complete .

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SDRAM Initialized state diagram ：

VIII. The following eight states and jump conditions are obtained according to the above analysis , Now we can SDRAM Initialize the module to design .

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Four 、SDRAM Automatically refresh

Through the sequence diagram , We summarize the automatic refresh as follows ：

1、 After initialization ,CKE pull up , And pre charge command
2、 wait for tRP Time , Send empty command during
3、tRP After time , Send auto refresh command , wait for tRFC Time , Send empty command during
4、tRFC After time , Send auto refresh command , Wait for tRFC Time , Send empty command during
5、 after tRFC After time , send out ACTIVE command

5、 ... and 、 Page burst read timing

Through the sequence diagram , We make the following summary of burst reading ：

1、 Send activation ACTIVE command , At the same time, the corresponding bank Address and line address
2、 wait for tRCD Time , Send empty command during
3、tRCD After time , Send read command , Appoint bank Address and column address
4、 Waiting column gating latency （CL = 2 individual clk）, Send empty command during
5、2 individual clk After that, you can see that the read data is presented on the data bus in turn , Complete the full page read operation .
6、Tn+2 moment , A burst termination command was issued , So full page reading is interrupted , thus , The burst length can be controlled by the burst termination command .
7、 After the burst read terminates , Send precharge command （ Manual precharge A10 pull up ）, Switch off all bank The line of , wait for tRP Time , Send empty command during ,tRP After time , A burst read operation is completed .

Be careful ： most SDRAM It does not support automatic pre charging in case of full page burst , Therefore, our read operation sequence includes manual precharge , That is, in the above summary 7
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reflection 1： Why read data in turn , Will be m,m+1,m+2, here we are m-1？
Therefore, the reading and writing of data are looped , For instance from 0 Start reading , One line is 512, So that is 0-511, If from 100 Start reading , So that is 100-511, Then there 0-99
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reflection 2： Why? Dout m-1 after , again m？
Because the full page burst cannot be automatically stopped , So we want it to stop , A burst termination command is required .

6、 ... and 、 Page burst write timing

1、 Send activation ACTIVE command , At the same time, the corresponding bank Address and line address
2、 wait for tRCD Time , Send empty command during
3、tRCD After time , Send write command , Specifies the written bank Address and column address
4、 Write without column gating latency , Until the write command is issued , The written data is output successively on the data bus .
5、 Keep writing , Complete the full page write operation .
6、 But in Tn+2 moment , A burst termination command was issued , So full page writing is interrupted .
7、 After the burst write is terminated , Send precharge command （ Manual precharge A10 pull up ）, Switch off all bank The line of , wait for tRP Time , Send empty command during ,tRP After time , A burst write operation is completed .

Reference resources