zcu102 PL端流水灯

详细操作步骤，请参考：https://blog.csdn.net/botao_li/article/details/85257566

本文仅增加部分注释。

#IO约束
set_property PACKAGE_PIN AL12 [get_ports {leds[7]}]
set_property PACKAGE_PIN AH14 [get_ports {leds[6]}]
set_property PACKAGE_PIN AH13 [get_ports {leds[5]}]
set_property PACKAGE_PIN AJ15 [get_ports {leds[4]}]
set_property PACKAGE_PIN AJ14 [get_ports {leds[3]}]
set_property PACKAGE_PIN AE13 [get_ports {leds[2]}]
set_property PACKAGE_PIN AF13 [get_ports {leds[1]}]
set_property PACKAGE_PIN AG14 [get_ports {leds[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[0]}]

set_property PACKAGE_PIN G21 [get_ports clk_p]
#set_property PACKAGE_PIN F21 [get_ports clk_n]
set_property IOSTANDARD LVDS_25 [get_ports clk_p]
set_property IOSTANDARD LVDS_25 [get_ports clk_n]

#时钟周期约束
#“create_clock”是该命令的名称，它会创建一个时钟；
# 其后的“-name clk_125_in”、“-period 8”、“[get_ports clk_p ]”都是该命令的各个参数，
# 分别表示所创建的时钟的名称是“clk_125_in”、时钟周期是 8ns、时钟源是 clk_p 端口
# -period 8.000  -waveform {0.000 4.000} ：代表的是时钟周期8ns，其中上升沿是在0ns的位置，下降沿是在4ns的位置
create_clock -period 8.000 -name clk_125_in -waveform {0.000 4.000} [get_ports clk_p]

相应的Verilog代码如下： 

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/01/06 19:17:04
// Design Name: 
// Module Name: pl_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module pl_top(
    input clk_p,
    input clk_n,
    output [7:0] leds
    );
    
    wire clk;//125MHz工作时钟
    
    //用原语实现差分时钟转单端
    IBUFDS
    #(
    .IOSTANDARD("DEFAULT")//DEFAULT默认所有情况
    )
    IBUFDS_inst
    (
    .O(clk),//输出
    .I(clk_p),//P端输入
    .IB(clk_n)//N端输入
    );
    
    //定义输出寄存器
    reg [7:0] leds = 8'b0000_0001;
    
    //计数器，计时1秒，计数范围0~27'd125_000_000-1
    reg [26:0] cnt = 27'd0;
    
    always @(posedge clk) begin
        case (cnt)
            27'd124_999_999: begin
                cnt <= 27'd0;//计数复位
                leds <= {leds[6:0], leds[7]};//循环移位
            end
            
            default: begin
                cnt <= cnt+27'd1;//计数
                leds <= leds;//保持
            end
        endcase
    end

endmodule