Test platform for combinational logic blocks

Test platform for combinational logic blocks

The test platform does not need to be integrated , therefore SystemVerilog All the syntax of can be used to write test platform . The modules of the test platform do not need to declare inputs and outputs , The test platform includes the tested objects 、 The signal source that generates the test excitation and the mechanism for observing or recording the output of the tested object .
The test platform usually implements two functions :1） Generate the input excitation required by the module under test :2） Check the output result of the tested module .

module adder #(parameter N = 4)
(
	output logic [N-1:0] Sum,
	output logic Count,
	input logic [N-1:0] A,B,
	input logic Cin
);

always_comb
	{Count,Sum} = A + B + Cin;
	
endmodule

module TestBitAdder;
 
parameter N = 4;
logic Cin ,Count;
logic [N-1:0] Sum,A,B;

adder #(N) s0(.*);

initial
begin
	Cin = '0;
	A = 4'b0000;
	B = 4'b0000;
	#5ns A = 4'b1111;
	#5ns Cin = '1;
	#5ns A = 4'b0111;
	#5ns B = 4'b1111;
	#5ns Cin = '0;
end

endmodule

Reference the adder in the instance adder when , Use a parameter (N) And a port that connects the excitation signal to the adder (*). Only when the network and variable names in the test platform are completely consistent with the port names of the modules referenced by the instances , This simplified port connection method is allowed .

Please note that , Time is relative , That is, wait after each assignment 5ns, Then assign the following statement . please remember , With keywords init