Modelsim simulation FFT core cannot be simulated solution (qsys)

One 、 Platform and environment

1、 Simulation environment ：ModelSim-altera 10.3

2、FPGA design environment ：Quartus ii 15.0

3、 operating system ：Windows 10

Two 、 Problem description

Recently, the author is debugging Altrera FPGA Self contained FFT nucleus , In the use of ModelSim The following error occurred during the simulation ：

Error message

Instantiation or 'FFT_out' failed.The design unit was not found.

It means ： Instantiation failed , This design unit cannot be found , Here is the search path . I found a lot of information on the Internet . These answers are almost the same ——1、 Need to add XXX.vo Files, not XXX.v file .2、 The related library is missing , To add manually ……

The version I used at that time was Quartus ii 16.0. I can't find a name in my project file XXX.vo The file of （ Actually, I found one .vo file , But not it ）. So I think it's my software problem , So I reinstalled 15.0 Version of , Sure enough , Or not? . And as a beginner , The missing library mentioned above , I also don't know what libraries other than the installation directory are referred to .

In the following , I found a document , It also records a solution , Just don't use it Quartus ii call ModelSim, Instead, add libraries manually , Then use it directly ModelSim Conduct door level simulation . But I still failed in this way , The reason is still that I can't find it .vo file . Then I built a new project , I noticed a bullet box that I had been ignoring , To solve the problem .

3、 ... and 、 terms of settlement

1、 First new IP nucleus , Although various versions of Qsys The interface of the tool is different , But they are all similar .

IP Nuclear interface

2、 Click... At the bottom right after setting Generate HDL. In the pop-up box ,simlation In the column of..., select verilog（ If you use VHDL If so, choose VHDL）, Click... When the selection is complete generate Generate IP nucleus . Click... After generation close close , Right click finish close Qsys Tools .

Setup page

3、 A box pops up , This is what I have been ignoring , The general meaning in the box is ： You generate a IP nucleus , But you need to add the following two files , These two files are XXX.qip and XXX.sip. Neither of these two files can be missing ！ The reason why the author reported an error in the simulation is that it was not added sip This file , Only added IP Nuclear documents .

Tips

4、 Last , Write a driver IP Nuclear documents , Then I'm writing a testbench file , stay settings--->simlation Inside, you can set what needs to be simulated testbench And then click RTL simlation The gate pole simulation can be carried out . Below I attach the relevant code .

 

FFT_test.v

module FFT_test(
        clk,                  
        rst_n,                   
        data_in,   //AD Collect data input 
        amp       //FFT The result of the calculation is 
    );
    input clk;
    input rst_n;
    input signed[11:0]data_in;
    output signed[24:0] amp;

    /**********  Definition FFT IP The core uses ports  **********/
    wire inverse;         //  Input , by 1 When an IFFT, by 0 When an FFT
    wire sink_ready;      //  Output ,FFT This signal is set when the engine is ready to receive data 
    wire source_ready;    //  Input , The downstream module sets the signal when data can be received 
    reg sink_valid;       //  Input , Effective marking signal ,sink_valid and sink_ready Start data transmission when both are set 
    reg sink_sop;         //  Input , High level means 1 Frame data loading starts 
    reg sink_eop;         //  Input , High level means 1 The loading of frame data ends 
    wire signed [11:0]sink_imag;  //  Input , Imaginary part of input data , Binary complement data 
    wire [1:0] sink_error;        //  Input , Indicates the loading data status , General arrangement 0
    wire [1:0] source_error;      //  Output , Express FFT Error in conversion 
    wire source_sop;              //  Output , A high level indicates the beginning of data conversion of one frame 
    wire source_eop;              //  Output , High level indicates the end of one frame data conversion 
    wire [5:0]source_exp;
    wire source_valid;
    wire signed [11:0] xkre;      //  Output , The real part of the output data , Binary complement data 
    wire signed [11:0] xkim;      //  Output , The imaginary part of the output data 

    assign sink_error = 2'b00;
    assign source_ready = 1'b1;   //  The signal is set to 1 Always ready to receive FFT data 
    assign inverse = 1'b0;        //  Conduct FFT Positive transformation 
    assign sink_imag = 12'd0;     //  Input data imaginary part is grounded 

    reg [10:0] count;        

    always @ (posedge clk or negedge rst_n)
        if (!rst_n) begin
            sink_eop <= 'b0;
            sink_sop <= 'b0;
            sink_valid <= 'b0;
            count <= 'b0;
        end
        else begin
            count <= count + 1'd1;
            if (count == 1) sink_sop <= 1'b1;   // Count 1, Set up sop, Start loading AD data 
            else  sink_sop <= 1'b0;

            if (count == 512) sink_eop <= 1'b1; 
            else  sink_eop <= 1'b0;

            if (count>=1 & count<=512) sink_valid <= 1'b1;  // During data loading , Set up sink_valid
            else  sink_valid <= 1'b0;
        end

    /**********  call IP Nuclear progress FFT Transformation ,Burst Pattern  **********/
    FFT u0 (
        .clk          (clk),              
        .reset_n      (rst_n),            
        .sink_valid   (sink_valid),       
        .sink_ready   (sink_ready),      
        .sink_error   (sink_error),      
        .sink_sop     (sink_sop),         
        .sink_eop     (sink_eop),         
        .sink_real    (data_in),          
        .sink_imag    (sink_imag),    

        .inverse      (inverse),      
        .source_valid (source_valid), 
        .source_ready (source_ready), 
        .source_error (source_error), 
        .source_sop   (source_sop),   
        .source_eop   (source_eop),  
        .source_exp   (source_exp),
        .source_real  (xkre),  
        .source_imag  (xkim)   
    );

    /**********  Calculate the amplitude signal of the spectrum  **********/
    wire signed [23:0] xkre_square, xkim_square;
    assign xkre_square = xkre * xkre;
    assign xkim_square = xkim * xkim;
    assign amp = xkre_square + xkim_square;

endmodule 

TB_test.v

`timescale 1ns/1ps// Clock scale 
`define clock_period 20// Macro defines clock scale 
module TB_test();

	reg clk;
	reg Rst_n;
	wire clk_100M;
	
	reg signed [11:0]data_in;
	wire signed [24:0]amp;

FFT_test FFT_0(
        .clk(clk),                     // The clock 
        .rst_n(Rst_n),                   // Low level effective reset 
        .data_in(data_in),   //AD Collect data input 
        .amp(amp)       //FFT The result of the calculation is 
    );
	

	initial clk = 1;
	always #(`clock_period/2) clk = ~clk;//50M The clock  ( Call the data defined by the macro divided by 2)

	initial begin
		Rst_n = 1'b0;// Reset 
		#200;
		Rst_n = 1'b1;// Reset complete 
		#2000000;
		$stop;// Stop simulation 
	end
	
	
reg [11:0]Count;
[email protected](posedge clk or negedge Rst_n)
if(!Rst_n)
	Count <= 12'd0;
else if(Count == 100)
	Count <= 12'd0;
else
	Count <= Count+1'd1;
//30M sampling  512 A sampling point  256 A high level  256 A low level 
[email protected](posedge clk or negedge Rst_n)
if(!Rst_n)
	data_in <= 12'd0;
else if(Count < 50)
	data_in <= 12'd0;
else
	data_in <= 12'HFF;
	

endmodule

Four 、 Simulation effect

Simulation effect

5、 ... and 、 summary

The author is also a little white who has not been in touch for a long time , This paper mainly records the use of Qsys Tool generated IP Some problems encountered in the nuclear simulation and the points I ignored . If you have any other questions, please point out , Learning together , Common progress .